DE69219372D1 - Mikrorechner mit Zeitüberwachungseinrichtung - Google Patents

Mikrorechner mit Zeitüberwachungseinrichtung

Info

Publication number
DE69219372D1
DE69219372D1 DE69219372T DE69219372T DE69219372D1 DE 69219372 D1 DE69219372 D1 DE 69219372D1 DE 69219372 T DE69219372 T DE 69219372T DE 69219372 T DE69219372 T DE 69219372T DE 69219372 D1 DE69219372 D1 DE 69219372D1
Authority
DE
Germany
Prior art keywords
microcomputer
monitoring device
time monitoring
time
monitoring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69219372T
Other languages
English (en)
Other versions
DE69219372T2 (de
Inventor
Tsuyoshi Katayose
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE69219372D1 publication Critical patent/DE69219372D1/de
Application granted granted Critical
Publication of DE69219372T2 publication Critical patent/DE69219372T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Debugging And Monitoring (AREA)
  • Microcomputers (AREA)
DE69219372T 1991-02-01 1992-02-03 Mikrorechner mit Zeitüberwachungseinrichtung Expired - Fee Related DE69219372T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3011827A JP2867717B2 (ja) 1991-02-01 1991-02-01 マイクロコンピュータ

Publications (2)

Publication Number Publication Date
DE69219372D1 true DE69219372D1 (de) 1997-06-05
DE69219372T2 DE69219372T2 (de) 1997-12-11

Family

ID=11788600

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69219372T Expired - Fee Related DE69219372T2 (de) 1991-02-01 1992-02-03 Mikrorechner mit Zeitüberwachungseinrichtung

Country Status (4)

Country Link
US (1) US5408643A (de)
EP (1) EP0497380B1 (de)
JP (1) JP2867717B2 (de)
DE (1) DE69219372T2 (de)

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JPH04306735A (ja) * 1991-04-04 1992-10-29 Toshiba Corp 非同期割込み禁止機構
JP2658697B2 (ja) * 1991-12-11 1997-09-30 富士通株式会社 ウォッチ・ドック・タイマ回路
US5530872A (en) * 1992-12-23 1996-06-25 International Business Machines Corporation Method and system for directing device driver to service multiple sequential interrupt requests generated by I/O device connected thereto
JPH08132992A (ja) * 1994-11-10 1996-05-28 Mitsubishi Electric Corp 車載用制御装置
US5541943A (en) * 1994-12-02 1996-07-30 At&T Corp. Watchdog timer lock-up prevention circuit
US5528756A (en) * 1995-01-30 1996-06-18 Elsag International N.V. Method and apparatus for performing supervisory functions in digital systems and obtaining diagnostics thereof
KR0177093B1 (ko) * 1995-05-31 1999-05-15 윤종용 Cpu 리셋회로
JP3357514B2 (ja) * 1995-09-20 2002-12-16 シャープ株式会社 暴走検出復帰方式
JPH09160807A (ja) * 1995-12-06 1997-06-20 Mitsuba Corp マイクロプロセッサの誤動作検出方法
US7266725B2 (en) 2001-09-03 2007-09-04 Pact Xpp Technologies Ag Method for debugging reconfigurable architectures
DE19651075A1 (de) 1996-12-09 1998-06-10 Pact Inf Tech Gmbh Einheit zur Verarbeitung von numerischen und logischen Operationen, zum Einsatz in Prozessoren (CPU's), Mehrrechnersystemen, Datenflußprozessoren (DFP's), digitalen Signal Prozessoren (DSP's) oder dergleichen
US5819095A (en) * 1996-12-20 1998-10-06 International Business Machines Corporation Method and apparatus for allowing an interrupt controller on an adapter to control a computer system
US5787290A (en) * 1996-12-20 1998-07-28 International Business Machines Corporation Adapter with an onboard interrupt controller for controlling a computer system
DE19654595A1 (de) 1996-12-20 1998-07-02 Pact Inf Tech Gmbh I0- und Speicherbussystem für DFPs sowie Bausteinen mit zwei- oder mehrdimensionaler programmierbaren Zellstrukturen
EP1329816B1 (de) 1996-12-27 2011-06-22 Richter, Thomas Verfahren zum selbständigen dynamischen Umladen von Datenflussprozessoren (DFPs) sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen (FPGAs, DPGAs, o.dgl.)
US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
JPH10269109A (ja) * 1997-03-21 1998-10-09 Mitsubishi Electric Corp マイクロコンピュータ
US6012154A (en) * 1997-09-18 2000-01-04 Intel Corporation Method and apparatus for detecting and recovering from computer system malfunction
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
US6393590B1 (en) * 1998-12-22 2002-05-21 Nortel Networks Limited Method and apparatus for ensuring proper functionality of a shared memory, multiprocessor system
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US6496890B1 (en) 1999-12-03 2002-12-17 Michael Joseph Azevedo Bus hang prevention and recovery for data communication systems employing a shared bus interface with multiple bus masters
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
DE10049441B4 (de) * 2000-10-06 2008-07-10 Conti Temic Microelectronic Gmbh Verfahren zum Betrieb eines von einem Prozessor gesteuerten Systems
DE10049440A1 (de) * 2000-10-06 2002-04-11 Daimler Chrysler Ag Verfahren zum Betrieb eines von einem Prozessor gesteuerten Systems
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7844796B2 (en) * 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7996827B2 (en) * 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
EP1351145A1 (de) * 2002-04-04 2003-10-08 Hewlett-Packard Company Rechnerfehlerbehebung und Notifizierungssystem
US20040015741A1 (en) * 2002-07-17 2004-01-22 Adc Telecommunications Israel Ltd. Watchdog device operation
EP1383047A1 (de) * 2002-07-18 2004-01-21 Cp8 Verfahren zur Sicherung der Ausführung eines Programms gegen Strahlungsangriffe oder ähnliches
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US20040034701A1 (en) * 2002-08-14 2004-02-19 Adc Dsl Systems, Inc. Watchdog termination in a communication system
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
US20040098573A1 (en) * 2002-11-18 2004-05-20 Adc Telecommunication Israel Ltd. Configurable initialization of hardware
US20040250178A1 (en) * 2003-05-23 2004-12-09 Munguia Peter R. Secure watchdog timer
CN100470498C (zh) * 2003-08-27 2009-03-18 皇家飞利浦电子股份有限公司 用于支撑和监视微控制器的电路装置和方法
JP4700611B2 (ja) * 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
CN100405307C (zh) * 2005-02-01 2008-07-23 艾默生网络能源有限公司 看门狗控制方法
FR2888370A1 (fr) * 2005-07-05 2007-01-12 St Microelectronics Sa Protection de l'execution d'un programme
EP1974265A1 (de) * 2006-01-18 2008-10-01 PACT XPP Technologies AG Hardwaredefinitionsverfahren
CN100397353C (zh) * 2006-07-26 2008-06-25 华为技术有限公司 一种提高单板异常处理能力的系统和方法
FR2910144A1 (fr) * 2006-12-18 2008-06-20 St Microelectronics Sa Procede et dispositif de detection errones au cours de l'execution d'un programme.
US7783872B2 (en) * 2007-03-30 2010-08-24 Dell Products, Lp System and method to enable an event timer in a multiple event timer operating environment
US9053233B2 (en) 2011-08-15 2015-06-09 Freescale Semiconductor, Inc. Method and device for controlling debug event resources
US9436627B2 (en) 2011-08-25 2016-09-06 International Business Machines Corporation Detection of abnormal operation caused by interrupt processing
WO2014175089A1 (ja) * 2013-04-26 2014-10-30 株式会社オートネットワーク技術研究所 フェイルセーフ回路
GB201405323D0 (en) * 2014-03-25 2014-05-07 Imagination Tech Ltd Prioritsing events to which a processor is to respond
CN104899125B (zh) * 2015-06-04 2019-01-29 新华三技术有限公司 一种单板系统的运行信息获取方法和装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656591B2 (ja) * 1981-07-06 1994-07-27 株式会社日立製作所 デ−タ編集処理装置
JPS60263235A (ja) * 1984-06-12 1985-12-26 Omron Tateisi Electronics Co マイクロコンピユ−タシステム
JPS6129239A (ja) * 1984-07-19 1986-02-10 Nec Corp プロセツサ異常再開方式
JPH0795291B2 (ja) * 1986-01-13 1995-10-11 沖電気工業株式会社 ウオツチドツグタイマ
US4726024A (en) * 1986-03-31 1988-02-16 Mieczyslaw Mirowski Fail safe architecture for a computer system
JPS6355601A (ja) * 1986-08-26 1988-03-10 Matsushita Electric Works Ltd ウオツチドツグタイマ回路
US4956842A (en) * 1988-11-16 1990-09-11 Sundstrand Corporation Diagnostic system for a watchdog timer

Also Published As

Publication number Publication date
EP0497380A2 (de) 1992-08-05
EP0497380B1 (de) 1997-05-02
EP0497380A3 (en) 1993-05-12
JP2867717B2 (ja) 1999-03-10
US5408643A (en) 1995-04-18
DE69219372T2 (de) 1997-12-11
JPH04246740A (ja) 1992-09-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee