DE69216138D1 - Verfahren zum Strukturieren mehrlagiger Dünnschichten mit einer supraleitenden Lage - Google Patents

Verfahren zum Strukturieren mehrlagiger Dünnschichten mit einer supraleitenden Lage

Info

Publication number
DE69216138D1
DE69216138D1 DE69216138T DE69216138T DE69216138D1 DE 69216138 D1 DE69216138 D1 DE 69216138D1 DE 69216138 T DE69216138 T DE 69216138T DE 69216138 T DE69216138 T DE 69216138T DE 69216138 D1 DE69216138 D1 DE 69216138D1
Authority
DE
Germany
Prior art keywords
structuring
thin films
superconducting layer
multilayer thin
multilayer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69216138T
Other languages
English (en)
Other versions
DE69216138T2 (de
Inventor
Hiroshi Inada
Michitomo Iiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP3103955A external-priority patent/JP2647277B2/ja
Priority claimed from JP3104655A external-priority patent/JP2647278B2/ja
Priority claimed from JP3104656A external-priority patent/JP2647279B2/ja
Priority claimed from JP3104657A external-priority patent/JP2647280B2/ja
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Publication of DE69216138D1 publication Critical patent/DE69216138D1/de
Application granted granted Critical
Publication of DE69216138T2 publication Critical patent/DE69216138T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0661—Processes performed after copper oxide formation, e.g. patterning
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/728—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S505/00—Superconductor technology: apparatus, material, process
    • Y10S505/725—Process of making or treating high tc, above 30 k, superconducting shaped material, article, or device
    • Y10S505/73—Vacuum treating or coating

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Superconductors And Manufacturing Methods Therefor (AREA)
DE69216138T 1991-04-09 1992-04-09 Verfahren zum Strukturieren mehrlagiger Dünnschichten mit einer supraleitenden Lage Expired - Fee Related DE69216138T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP3103955A JP2647277B2 (ja) 1991-04-09 1991-04-09 積層膜の作製方法
JP3104655A JP2647278B2 (ja) 1991-04-10 1991-04-10 積層膜の作製方法
JP3104656A JP2647279B2 (ja) 1991-04-10 1991-04-10 積層膜の作製方法
JP3104657A JP2647280B2 (ja) 1991-04-10 1991-04-10 積層膜の作製方法

Publications (2)

Publication Number Publication Date
DE69216138D1 true DE69216138D1 (de) 1997-02-06
DE69216138T2 DE69216138T2 (de) 1997-06-19

Family

ID=27469169

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69216138T Expired - Fee Related DE69216138T2 (de) 1991-04-09 1992-04-09 Verfahren zum Strukturieren mehrlagiger Dünnschichten mit einer supraleitenden Lage

Country Status (4)

Country Link
US (1) US5326747A (de)
EP (1) EP0509886B1 (de)
CA (1) CA2065625C (de)
DE (1) DE69216138T2 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08501416A (ja) * 1992-09-14 1996-02-13 コンダクタス・インコーポレーテッド 酸化物超伝導体装置及び回路のための改善されたバリア層
JP2822953B2 (ja) * 1995-09-14 1998-11-11 日本電気株式会社 超伝導回路の製造方法
US6541136B1 (en) * 1998-09-14 2003-04-01 The Regents Of The University Of California Superconducting structure

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2626715B1 (fr) * 1988-02-02 1990-05-18 Thomson Csf Dispositif en couches minces de materiau supraconducteur et procede de realisation
JPH01230275A (ja) * 1988-03-10 1989-09-13 Mitsubishi Metal Corp 超電導薄膜の形成法
JPH0772337B2 (ja) * 1988-10-27 1995-08-02 株式会社フジクラ 酸化物超電導体の製造方法
DE69026301T2 (de) * 1989-05-12 1996-09-05 Matsushita Electric Ind Co Ltd Supraleitende Einrichtung und deren Herstellungsverfahren
US5147849A (en) * 1989-09-20 1992-09-15 Sumitomo Electric Industries, Ltd. Electrode for electrical connection to oxide superconductor and method for forming the same
US5084437A (en) * 1990-02-28 1992-01-28 Westinghouse Electric Corp. Method for making high-current, ohmic contacts between semiconductors and oxide superconductors
US5132796A (en) * 1990-09-04 1992-07-21 Matsushita Electric Industrial Co., Ltd. Method and apparatus for digitally processing gamma pedestal and gain
JPH0563247A (ja) * 1990-09-18 1993-03-12 Sumitomo Electric Ind Ltd 超電導接合構造体およびその作製方法

Also Published As

Publication number Publication date
CA2065625A1 (en) 1992-10-10
EP0509886A2 (de) 1992-10-21
CA2065625C (en) 1997-07-01
US5326747A (en) 1994-07-05
EP0509886B1 (de) 1996-12-27
DE69216138T2 (de) 1997-06-19
EP0509886A3 (en) 1993-01-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee