DE69131682T2 - Musterherstellungssystem - Google Patents

Musterherstellungssystem

Info

Publication number
DE69131682T2
DE69131682T2 DE69131682T DE69131682T DE69131682T2 DE 69131682 T2 DE69131682 T2 DE 69131682T2 DE 69131682 T DE69131682 T DE 69131682T DE 69131682 T DE69131682 T DE 69131682T DE 69131682 T2 DE69131682 T2 DE 69131682T2
Authority
DE
Germany
Prior art keywords
making system
pattern making
pattern
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131682T
Other languages
English (en)
Other versions
DE69131682D1 (de
Inventor
Hatsuo Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE69131682D1 publication Critical patent/DE69131682D1/de
Publication of DE69131682T2 publication Critical patent/DE69131682T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
DE69131682T 1990-12-19 1991-12-18 Musterherstellungssystem Expired - Fee Related DE69131682T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2403792A JP2577507B2 (ja) 1990-12-19 1990-12-19 ウェーハの描画装置

Publications (2)

Publication Number Publication Date
DE69131682D1 DE69131682D1 (de) 1999-11-11
DE69131682T2 true DE69131682T2 (de) 2000-03-09

Family

ID=18513522

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131682T Expired - Fee Related DE69131682T2 (de) 1990-12-19 1991-12-18 Musterherstellungssystem

Country Status (5)

Country Link
US (1) US5305222A (de)
EP (1) EP0491375B1 (de)
JP (1) JP2577507B2 (de)
KR (1) KR950003892B1 (de)
DE (1) DE69131682T2 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3336649B2 (ja) * 1992-12-25 2002-10-21 株式会社ニコン 露光装置、露光方法、及びその露光方法を含むデバイス製造方法、及びそのデバイス製造方法により製造されたデバイス
JPH07211622A (ja) * 1994-01-27 1995-08-11 Nikon Corp 露光方法及び露光システム
JP3058245B2 (ja) * 1995-01-27 2000-07-04 キヤノン株式会社 投影露光装置及び半導体製造方法
US5699260A (en) * 1995-03-14 1997-12-16 Analog Devices, Incorporated Technique for optimizing the number of IC chips obtainable from a wafer
JP3320262B2 (ja) * 1995-07-07 2002-09-03 キヤノン株式会社 走査露光装置及び方法並びにそれを用いたデバイス製造方法
DE19537756A1 (de) * 1995-10-10 1997-04-17 Itt Ind Gmbh Deutsche Verfahren zum Optimieren einer Stepfeldanordnung auf einem Halbleiterwafer
JPH09190971A (ja) * 1995-10-10 1997-07-22 Deutsche Itt Ind Gmbh 半導体ウエハにおけるチップパタンの最適化方法
KR100219699B1 (ko) * 1995-10-30 1999-09-01 손욱 음극선관
US6021267A (en) * 1997-09-08 2000-02-01 International Business Machines Corporation Aspect ratio program for optimizing semiconductor chip shape
US6604233B1 (en) 1999-06-28 2003-08-05 Texas Instruments Incorporated Method for optimizing the integrated circuit chip size for efficient manufacturing
US6374398B1 (en) * 1999-12-28 2002-04-16 Vlsi Technology, Inc. Efficient database for die-per-wafer computations
US6529790B1 (en) * 1999-12-28 2003-03-04 Koninklijke Philips Electronics N.V. Computation of die-per-wafer considering production technology and wafer size
US6522940B1 (en) * 1999-12-28 2003-02-18 Koninklijke Philips Electronics N.V. Method and system for varying die shape to increase wafer productivity
US6980917B2 (en) * 2002-12-30 2005-12-27 Lsi Logic Corporation Optimization of die yield in a silicon wafer “sweet spot”
US7243325B2 (en) * 2004-07-21 2007-07-10 Bae Systems Information And Electronic Systems Integration Inc. Method and apparatus for generating a wafer map
US7353077B2 (en) * 2005-07-29 2008-04-01 Taiwan Semiconductor Manufacturing Company Methods for optimizing die placement
DE102007030051B4 (de) 2007-06-29 2018-05-30 Globalfoundries Inc. Waferlayout-Optimierungsverfahren und System
CN112446887B (zh) * 2019-09-05 2022-04-08 长鑫存储技术有限公司 晶圆切割晶片数计算方法及计算设备
EP3992715B1 (de) * 2020-09-09 2023-05-31 Changxin Memory Technologies, Inc. Verfahren, medium und vorrichtung zur berechnung eines waferchip-layouts
CN114239467A (zh) * 2020-09-09 2022-03-25 长鑫存储技术有限公司 晶圆的晶片布局计算方法、装置、介质与设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58107633A (ja) * 1981-12-21 1983-06-27 Canon Inc 特殊チツプを逃げたシヨツト配列方法
JPS59101831A (ja) * 1982-12-01 1984-06-12 Canon Inc 半導体焼付露光装置
US4734746A (en) * 1985-06-24 1988-03-29 Nippon Kogaku K. K. Exposure method and system for photolithography

Also Published As

Publication number Publication date
KR950003892B1 (ko) 1995-04-20
EP0491375A3 (en) 1992-10-28
JPH04218908A (ja) 1992-08-10
EP0491375A2 (de) 1992-06-24
KR920013644A (ko) 1992-07-29
EP0491375B1 (de) 1999-10-06
DE69131682D1 (de) 1999-11-11
US5305222A (en) 1994-04-19
JP2577507B2 (ja) 1997-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee