DE69130652D1 - Digitaler paralleler Hochgeschwindigkeitsmultiplizierer - Google Patents

Digitaler paralleler Hochgeschwindigkeitsmultiplizierer

Info

Publication number
DE69130652D1
DE69130652D1 DE69130652T DE69130652T DE69130652D1 DE 69130652 D1 DE69130652 D1 DE 69130652D1 DE 69130652 T DE69130652 T DE 69130652T DE 69130652 T DE69130652 T DE 69130652T DE 69130652 D1 DE69130652 D1 DE 69130652D1
Authority
DE
Germany
Prior art keywords
high speed
digital high
speed parallel
parallel multiplier
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69130652T
Other languages
English (en)
Other versions
DE69130652T2 (de
Inventor
Gensuke Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2072384A external-priority patent/JPH081593B2/ja
Priority claimed from JP3013629A external-priority patent/JP2525083B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE69130652D1 publication Critical patent/DE69130652D1/de
Application granted granted Critical
Publication of DE69130652T2 publication Critical patent/DE69130652T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/53—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel
    • G06F7/5318—Multiplying only in parallel-parallel fashion, i.e. both operands being entered in parallel with column wise addition of partial products, e.g. using Wallace tree, Dadda counters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
    • G06F7/5334—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product
    • G06F7/5336—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm
    • G06F7/5338—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even by using multiple bit scanning, i.e. by decoding groups of successive multiplier bits in order to select an appropriate precalculated multiple of the multiplicand as a partial product overlapped, i.e. with successive bitgroups sharing one or more bits being recoded into signed digit representation, e.g. using the Modified Booth Algorithm each bitgroup having two new bits, e.g. 2nd order MBA

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Complex Calculations (AREA)
DE69130652T 1990-03-20 1991-03-20 Digitaler paralleler Hochgeschwindigkeitsmultiplizierer Expired - Fee Related DE69130652T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2072384A JPH081593B2 (ja) 1990-03-20 1990-03-20 乗算器
JP3013629A JP2525083B2 (ja) 1991-02-05 1991-02-05 乗算器

Publications (2)

Publication Number Publication Date
DE69130652D1 true DE69130652D1 (de) 1999-02-04
DE69130652T2 DE69130652T2 (de) 1999-05-06

Family

ID=26349445

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69130652T Expired - Fee Related DE69130652T2 (de) 1990-03-20 1991-03-20 Digitaler paralleler Hochgeschwindigkeitsmultiplizierer

Country Status (4)

Country Link
US (1) US5465226A (de)
EP (1) EP0448367B1 (de)
KR (1) KR940002479B1 (de)
DE (1) DE69130652T2 (de)

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JP2600591B2 (ja) * 1993-11-19 1997-04-16 日本電気株式会社 乗算器
FR2722590B1 (fr) * 1994-07-15 1996-09-06 Sgs Thomson Microelectronics Circuit logique de multiplication parallele
US5771186A (en) * 1995-06-07 1998-06-23 International Business Machines System and method for multiplying in a data processing system
US5754459A (en) * 1996-02-08 1998-05-19 Xilinx, Inc. Multiplier circuit design for a programmable logic device
JP3532338B2 (ja) * 1996-02-27 2004-05-31 株式会社ルネサステクノロジ 乗算装置
JP3652447B2 (ja) * 1996-07-24 2005-05-25 株式会社ルネサステクノロジ ツリー回路
KR19990079024A (ko) 1998-03-04 1999-11-05 김영환 병렬 승산기
US6434587B1 (en) 1999-06-14 2002-08-13 Intel Corporation Fast 16-B early termination implementation for 32-B multiply-accumulate unit
US7119576B1 (en) 2000-09-18 2006-10-10 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
US7346644B1 (en) 2000-09-18 2008-03-18 Altera Corporation Devices and methods with programmable logic and digital signal processing regions
JP2005182238A (ja) * 2003-12-17 2005-07-07 Renesas Technology Corp 演算装置
US7506017B1 (en) 2004-05-25 2009-03-17 Altera Corporation Verifiable multimode multipliers
US7565391B2 (en) * 2004-12-17 2009-07-21 The Regents Of The University Of California Binary digit multiplications and applications
US8620980B1 (en) 2005-09-27 2013-12-31 Altera Corporation Programmable device with specialized multiplier blocks
US8301681B1 (en) 2006-02-09 2012-10-30 Altera Corporation Specialized processing block for programmable logic device
US8266198B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US8041759B1 (en) 2006-02-09 2011-10-18 Altera Corporation Specialized processing block for programmable logic device
US8266199B2 (en) 2006-02-09 2012-09-11 Altera Corporation Specialized processing block for programmable logic device
US7836117B1 (en) 2006-04-07 2010-11-16 Altera Corporation Specialized processing block for programmable logic device
US7822799B1 (en) 2006-06-26 2010-10-26 Altera Corporation Adder-rounder circuitry for specialized processing block in programmable logic device
US8386550B1 (en) 2006-09-20 2013-02-26 Altera Corporation Method for configuring a finite impulse response filter in a programmable logic device
US8386553B1 (en) 2006-12-05 2013-02-26 Altera Corporation Large multiplier for programmable logic device
US7930336B2 (en) 2006-12-05 2011-04-19 Altera Corporation Large multiplier for programmable logic device
US7814137B1 (en) 2007-01-09 2010-10-12 Altera Corporation Combined interpolation and decimation filter for programmable logic device
US8650231B1 (en) 2007-01-22 2014-02-11 Altera Corporation Configuring floating point operations in a programmable device
US7865541B1 (en) 2007-01-22 2011-01-04 Altera Corporation Configuring floating point operations in a programmable logic device
US8645450B1 (en) 2007-03-02 2014-02-04 Altera Corporation Multiplier-accumulator circuitry and methods
US7949699B1 (en) 2007-08-30 2011-05-24 Altera Corporation Implementation of decimation filter in integrated circuit device using ram-based data storage
US8959137B1 (en) 2008-02-20 2015-02-17 Altera Corporation Implementing large multipliers in a programmable integrated circuit device
US8244789B1 (en) 2008-03-14 2012-08-14 Altera Corporation Normalization of floating point operations in a programmable integrated circuit device
US8626815B1 (en) 2008-07-14 2014-01-07 Altera Corporation Configuring a programmable integrated circuit device to perform matrix multiplication
US8255448B1 (en) 2008-10-02 2012-08-28 Altera Corporation Implementing division in a programmable integrated circuit device
US8307023B1 (en) 2008-10-10 2012-11-06 Altera Corporation DSP block for implementing large multiplier on a programmable integrated circuit device
US8886696B1 (en) 2009-03-03 2014-11-11 Altera Corporation Digital signal processing circuitry with redundancy and ability to support larger multipliers
US8805916B2 (en) 2009-03-03 2014-08-12 Altera Corporation Digital signal processing circuitry with redundancy and bidirectional data paths
US8706790B1 (en) 2009-03-03 2014-04-22 Altera Corporation Implementing mixed-precision floating-point operations in a programmable integrated circuit device
US8645449B1 (en) 2009-03-03 2014-02-04 Altera Corporation Combined floating point adder and subtractor
US8549055B2 (en) 2009-03-03 2013-10-01 Altera Corporation Modular digital signal processing circuitry with optionally usable, dedicated connections between modules of the circuitry
US8468192B1 (en) 2009-03-03 2013-06-18 Altera Corporation Implementing multipliers in a programmable integrated circuit device
US8650236B1 (en) 2009-08-04 2014-02-11 Altera Corporation High-rate interpolation or decimation filter in integrated circuit device
US8396914B1 (en) 2009-09-11 2013-03-12 Altera Corporation Matrix decomposition in an integrated circuit device
US8412756B1 (en) 2009-09-11 2013-04-02 Altera Corporation Multi-operand floating point operations in a programmable integrated circuit device
US7948267B1 (en) 2010-02-09 2011-05-24 Altera Corporation Efficient rounding circuits and methods in configurable integrated circuit devices
US8539016B1 (en) 2010-02-09 2013-09-17 Altera Corporation QR decomposition in an integrated circuit device
US8601044B2 (en) 2010-03-02 2013-12-03 Altera Corporation Discrete Fourier Transform in an integrated circuit device
US8458243B1 (en) 2010-03-03 2013-06-04 Altera Corporation Digital signal processing circuit blocks with support for systolic finite-impulse-response digital filtering
US8484265B1 (en) 2010-03-04 2013-07-09 Altera Corporation Angular range reduction in an integrated circuit device
US8510354B1 (en) 2010-03-12 2013-08-13 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8539014B2 (en) 2010-03-25 2013-09-17 Altera Corporation Solving linear matrices in an integrated circuit device
US8589463B2 (en) 2010-06-25 2013-11-19 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8862650B2 (en) 2010-06-25 2014-10-14 Altera Corporation Calculation of trigonometric functions in an integrated circuit device
US8577951B1 (en) 2010-08-19 2013-11-05 Altera Corporation Matrix operations in an integrated circuit device
US8645451B2 (en) 2011-03-10 2014-02-04 Altera Corporation Double-clocked specialized processing block in an integrated circuit device
US9600278B1 (en) 2011-05-09 2017-03-21 Altera Corporation Programmable device using fixed and configurable logic to implement recursive trees
US8812576B1 (en) 2011-09-12 2014-08-19 Altera Corporation QR decomposition in an integrated circuit device
US9053045B1 (en) 2011-09-16 2015-06-09 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8949298B1 (en) 2011-09-16 2015-02-03 Altera Corporation Computing floating-point polynomials in an integrated circuit device
US8762443B1 (en) 2011-11-15 2014-06-24 Altera Corporation Matrix operations in an integrated circuit device
US8543634B1 (en) 2012-03-30 2013-09-24 Altera Corporation Specialized processing block for programmable integrated circuit device
US9098332B1 (en) 2012-06-01 2015-08-04 Altera Corporation Specialized processing block with fixed- and floating-point structures
US8996600B1 (en) 2012-08-03 2015-03-31 Altera Corporation Specialized processing block for implementing floating-point multiplier with subnormal operation support
US9207909B1 (en) 2012-11-26 2015-12-08 Altera Corporation Polynomial calculations optimized for programmable integrated circuit device structures
US9189200B1 (en) 2013-03-14 2015-11-17 Altera Corporation Multiple-precision processing block in a programmable integrated circuit device
US9348795B1 (en) 2013-07-03 2016-05-24 Altera Corporation Programmable device using fixed and configurable logic to implement floating-point rounding
US9379687B1 (en) 2014-01-14 2016-06-28 Altera Corporation Pipelined systolic finite impulse response filter
US9684488B2 (en) 2015-03-26 2017-06-20 Altera Corporation Combined adder and pre-adder for high-radix multiplier circuit
US10089110B2 (en) * 2016-07-02 2018-10-02 Intel Corporation Systems, apparatuses, and methods for cumulative product
US10942706B2 (en) 2017-05-05 2021-03-09 Intel Corporation Implementation of floating-point trigonometric functions in an integrated circuit device
US11269629B2 (en) 2018-11-29 2022-03-08 The Regents Of The University Of Michigan SRAM-based process in memory system

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US4168530A (en) * 1978-02-13 1979-09-18 Burroughs Corporation Multiplication circuit using column compression
JPS55105732A (en) * 1979-02-08 1980-08-13 Nippon Telegr & Teleph Corp <Ntt> Multiplier
US4545028A (en) * 1982-10-13 1985-10-01 Hewlett-Packard Company Partial product accumulation in high performance multipliers
JPS60237534A (ja) * 1984-05-09 1985-11-26 Toshiba Corp 並列乗算器
JPS61114338A (ja) * 1984-11-09 1986-06-02 Hitachi Ltd 乗算器
US4748582A (en) * 1985-06-19 1988-05-31 Advanced Micro Devices, Inc. Parallel multiplier array with foreshortened sign extension
US4745570A (en) * 1986-05-27 1988-05-17 International Business Machines Corporation Binary multibit multiplier
JPS6355627A (ja) * 1986-08-27 1988-03-10 Toshiba Corp 半導体論理演算装置
JPH01134527A (ja) * 1987-11-19 1989-05-26 Mitsubishi Electric Corp 乗算器
DE3823722A1 (de) * 1988-07-13 1990-01-18 Siemens Ag Multiplizierer

Also Published As

Publication number Publication date
EP0448367A3 (en) 1993-01-07
DE69130652T2 (de) 1999-05-06
US5465226A (en) 1995-11-07
EP0448367B1 (de) 1998-12-23
EP0448367A2 (de) 1991-09-25
KR940002479B1 (ko) 1994-03-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee