DE69111707D1 - Fehlerübergangsmodus für eine Mehrrechneranordnung. - Google Patents

Fehlerübergangsmodus für eine Mehrrechneranordnung.

Info

Publication number
DE69111707D1
DE69111707D1 DE69111707T DE69111707T DE69111707D1 DE 69111707 D1 DE69111707 D1 DE 69111707D1 DE 69111707 T DE69111707 T DE 69111707T DE 69111707 T DE69111707 T DE 69111707T DE 69111707 D1 DE69111707 D1 DE 69111707D1
Authority
DE
Germany
Prior art keywords
transfer mode
computer arrangement
error transfer
error
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69111707T
Other languages
English (en)
Other versions
DE69111707T2 (de
Inventor
Rebecca L Stamm
Raymond Strouble
R Iris Bahar
Michael Callander
Linda Chao
Derrick Meyer
Douglas Sanders
Richard L Sites
Nicholas Wade
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE69111707D1 publication Critical patent/DE69111707D1/de
Publication of DE69111707T2 publication Critical patent/DE69111707T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0804—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with main memory updating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F02—COMBUSTION ENGINES; HOT-GAS OR COMBUSTION-PRODUCT ENGINE PLANTS
    • F02B—INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL
    • F02B75/00—Other engines
    • F02B75/02—Engines characterised by their cycles, e.g. six-stroke
    • F02B2075/022—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle
    • F02B2075/025—Engines characterised by their cycles, e.g. six-stroke having less than six strokes per cycle two
DE69111707T 1990-06-29 1991-06-27 Fehlerübergangsmodus für eine Mehrrechneranordnung. Expired - Lifetime DE69111707T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/547,597 US5155843A (en) 1990-06-29 1990-06-29 Error transition mode for multi-processor system

Publications (2)

Publication Number Publication Date
DE69111707D1 true DE69111707D1 (de) 1995-09-07
DE69111707T2 DE69111707T2 (de) 1996-03-28

Family

ID=24185305

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69111707T Expired - Lifetime DE69111707T2 (de) 1990-06-29 1991-06-27 Fehlerübergangsmodus für eine Mehrrechneranordnung.

Country Status (5)

Country Link
US (1) US5155843A (de)
EP (1) EP0465319B1 (de)
JP (1) JPH0695964A (de)
CA (1) CA2045715A1 (de)
DE (1) DE69111707T2 (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113703365A (zh) * 2021-08-26 2021-11-26 北京无线电测量研究所 设备监测信息的管理方法及系统

Families Citing this family (89)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2993975B2 (ja) * 1989-08-23 1999-12-27 株式会社リコー 中央演算処理装置
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US5404482A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
EP0463965B1 (de) * 1990-06-29 1998-09-09 Digital Equipment Corporation Sprungvorhersageeinheit für hochleistungsfähigen Prozessor
US5347648A (en) * 1990-06-29 1994-09-13 Digital Equipment Corporation Ensuring write ordering under writeback cache error conditions
US5404483A (en) * 1990-06-29 1995-04-04 Digital Equipment Corporation Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills
US5276852A (en) * 1990-10-01 1994-01-04 Digital Equipment Corporation Method and apparatus for controlling a processor bus used by multiple processor components during writeback cache transactions
JPH04184534A (ja) * 1990-11-20 1992-07-01 Fujitsu Ltd プロセッサ
DE69229081T2 (de) * 1991-03-01 2000-01-05 Advanced Micro Devices Inc Mikroprozessor mit externem Speicher
US5261071A (en) * 1991-03-21 1993-11-09 Control Data System, Inc. Dual pipe cache memory with out-of-order issue capability
US5293603A (en) * 1991-06-04 1994-03-08 Intel Corporation Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path
US5392417A (en) * 1991-06-05 1995-02-21 Intel Corporation Processor cycle tracking in a controller for two-way set associative cache
US5325494A (en) * 1991-06-21 1994-06-28 Kabushiki Kaisha Toshiba Computer
JP2984463B2 (ja) * 1991-06-24 1999-11-29 株式会社日立製作所 マイクロコンピュータ
US7197623B1 (en) 1991-06-27 2007-03-27 Texas Instruments Incorporated Multiple processor cellular radio
FR2678400B1 (fr) * 1991-06-27 1995-08-04 Texas Instruments France Processeur de protocole destine a l'execution d'un ensemble d'instructions en un nombre reduit d'operation.
US5319760A (en) * 1991-06-28 1994-06-07 Digital Equipment Corporation Translation buffer for virtual machines with address space match
US5539911A (en) 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
US5493687A (en) 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
JPH0520066A (ja) * 1991-07-16 1993-01-29 Mitsubishi Electric Corp 並列計算機
US5459849A (en) * 1991-08-02 1995-10-17 International Business Machines Corporation Method and apparatus for compressing cacheable data
US5530835A (en) * 1991-09-18 1996-06-25 Ncr Corporation Computer memory data merging technique for computers with write-back caches
EP0547769B1 (de) * 1991-12-18 1999-10-13 Sun Microsystems, Inc. Schreibüberlappung mit Verhinderung des Überschreibens
GB2277181B (en) * 1991-12-23 1995-12-13 Intel Corp Interleaved cache for multiple accesses per clock in a microprocessor
JP2762829B2 (ja) * 1992-02-06 1998-06-04 日本電気株式会社 電子計算機
US5438668A (en) * 1992-03-31 1995-08-01 Seiko Epson Corporation System and method for extraction, alignment and decoding of CISC instructions into a nano-instruction bucket for execution by a RISC computer
WO1993020505A2 (en) 1992-03-31 1993-10-14 Seiko Epson Corporation Superscalar risc instruction scheduling
US5629950A (en) * 1992-04-24 1997-05-13 Digital Equipment Corporation Fault management scheme for a cache memory
US5918029A (en) * 1996-09-27 1999-06-29 Digital Equipment Corporation Bus interface slicing mechanism allowing for a control/data-path slice
US5319766A (en) * 1992-04-24 1994-06-07 Digital Equipment Corporation Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
JP3637920B2 (ja) 1992-05-01 2005-04-13 セイコーエプソン株式会社 スーパースケーラマイクロプロセサに於て命令をリタイアさせるシステム及び方法
US5418973A (en) * 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
US5355471A (en) * 1992-08-14 1994-10-11 Pyramid Technology Corporation Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort
US6735685B1 (en) 1992-09-29 2004-05-11 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
KR100248903B1 (ko) * 1992-09-29 2000-03-15 야스카와 히데아키 수퍼스칼라마이크로프로세서에서의 적재 및 저장연산처리방법 및 시스템
EP0596144A1 (de) * 1992-10-07 1994-05-11 International Business Machines Corporation Hierarchises Speichersystem für Mikrokode und Vorrichtung zur Korrektur von Fehlern in der Mikrokode
JPH06187257A (ja) * 1992-12-17 1994-07-08 Fujitsu Ltd システムバス制御方式
DE69330889T2 (de) 1992-12-31 2002-03-28 Seiko Epson Corp System und Verfahren zur Änderung der Namen von Registern
US5628021A (en) 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
US5568415A (en) * 1993-02-19 1996-10-22 Digital Equipment Corporation Content addressable memory having a pair of memory cells storing don't care states for address translation
US5577217A (en) * 1993-05-14 1996-11-19 Intel Corporation Method and apparatus for a branch target buffer with shared branch pattern tables for associated branch predictions
JP3230898B2 (ja) * 1993-06-02 2001-11-19 シャープ株式会社 データ駆動型情報処理システム
US5406504A (en) * 1993-06-30 1995-04-11 Digital Equipment Multiprocessor cache examiner and coherency checker
JPH0756815A (ja) * 1993-07-28 1995-03-03 Internatl Business Mach Corp <Ibm> キャッシュ動作方法及びキャッシュ
US5671372A (en) * 1993-09-30 1997-09-23 International Business Machines Corporation Data processing system with microprocessor/cache chip set directly coupled to memory bus of narrower data width
US5918046A (en) * 1994-01-03 1999-06-29 Intel Corporation Method and apparatus for a branch instruction pointer table
US5515522A (en) * 1994-02-24 1996-05-07 Hewlett-Packard Company Coherence index generation for use by an input/output adapter located outside of the processor to detect whether the updated version of data resides within the cache
JPH07334416A (ja) * 1994-06-06 1995-12-22 Internatl Business Mach Corp <Ibm> コンピュータ・システムにおけるページ・モード・メモリの初期設定の方法および手段
US5636359A (en) * 1994-06-20 1997-06-03 International Business Machines Corporation Performance enhancement system and method for a hierarchical data cache using a RAID parity scheme
US5634073A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
US5644759A (en) * 1995-01-19 1997-07-01 Unisys Corporation Apparatus and method for processing a jump instruction preceded by a skip instruction
JP2731745B2 (ja) * 1995-03-23 1998-03-25 甲府日本電気株式会社 データ障害処理装置
US5802340A (en) * 1995-08-22 1998-09-01 International Business Machines Corporation Method and system of executing speculative store instructions in a parallel processing computer system
US5926642A (en) * 1995-10-06 1999-07-20 Advanced Micro Devices, Inc. RISC86 instruction set
US5815648A (en) * 1995-11-14 1998-09-29 Eccs, Inc. Apparatus and method for changing the cache mode dynamically in a storage array system
US5758065A (en) * 1995-11-30 1998-05-26 Ncr Corporation System and method of establishing error precedence in a computer system
US5983329A (en) * 1996-05-03 1999-11-09 Sun Microsystems, Inc. Caching virtual memory locks
US5815688A (en) * 1996-10-09 1998-09-29 Hewlett-Packard Company Verification of accesses in a functional model of a speculative out-of-order computer system
US5784394A (en) * 1996-11-15 1998-07-21 International Business Machines Corporation Method and system for implementing parity error recovery schemes in a data processing system
US5895486A (en) * 1996-12-20 1999-04-20 International Business Machines Corporation Method and system for selectively invalidating cache lines during multiple word store operations for memory coherence
US6581126B1 (en) * 1996-12-20 2003-06-17 Plx Technology, Inc. Method, system and apparatus for a computer subsystem interconnection using a chain of bus repeaters
US6088793A (en) * 1996-12-30 2000-07-11 Intel Corporation Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor
US5878242A (en) * 1997-04-21 1999-03-02 International Business Machines Corporation Method and system for forwarding instructions in a processor with increased forwarding probability
US6216218B1 (en) * 1997-11-03 2001-04-10 Donald L. Sollars Processor having a datapath and control logic constituted with basis execution blocks
US6425060B1 (en) * 1999-01-05 2002-07-23 International Business Machines Corporation Circuit arrangement and method with state-based transaction scheduling
US6704856B1 (en) * 1999-02-01 2004-03-09 Hewlett-Packard Development Company, L.P. Method for compacting an instruction queue
US6738896B1 (en) 1999-02-01 2004-05-18 Hewlett-Packard Development Company, L.P. Method and apparatus for determining availability of a queue which allows random insertion
US6542987B1 (en) * 1999-02-01 2003-04-01 Hewlett-Packard Development Company L.P. Method and circuits for early detection of a full queue
US6321303B1 (en) * 1999-03-18 2001-11-20 International Business Machines Corporation Dynamically modifying queued transactions in a cache memory system
US7039750B1 (en) 2001-07-24 2006-05-02 Plx Technology, Inc. On-chip switch fabric
US6850999B1 (en) * 2002-11-27 2005-02-01 Cisco Technology, Inc. Coherency coverage of data across multiple packets varying in sizes
JP4368587B2 (ja) * 2003-01-14 2009-11-18 富士通株式会社 バスブリッジ回路、バス接続システム、及びバスブリッジ回路のデータエラー通知方法
US7233880B2 (en) * 2003-09-11 2007-06-19 Intel Corporation Adaptive cache algorithm for temperature sensitive memory
US20050278505A1 (en) * 2004-05-19 2005-12-15 Lim Seow C Microprocessor architecture including zero impact predictive data pre-fetch mechanism for pipeline data memory
US20060179382A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Method and circuit for implementing array bypass operations without access penalty
US7797610B1 (en) * 2005-07-19 2010-09-14 Xilinx, Inc. Method and apparatus for virtual quad-port random access memory
US20070074007A1 (en) 2005-09-28 2007-03-29 Arc International (Uk) Limited Parameterizable clip instruction and method of performing a clip operation using the same
JP4882625B2 (ja) * 2005-12-26 2012-02-22 株式会社デンソー マイクロコンピュータ
US7454596B2 (en) * 2006-06-29 2008-11-18 Intel Corporation Method and apparatus for partitioned pipelined fetching of multiple execution threads
US20080162805A1 (en) * 2007-01-03 2008-07-03 Springfield Randall S Method and Apparatus for Using Non-Addressable Memories of a Computer System
US7711935B2 (en) * 2007-04-30 2010-05-04 Netlogic Microsystems, Inc. Universal branch identifier for invalidation of speculative instructions
US11768689B2 (en) 2013-08-08 2023-09-26 Movidius Limited Apparatus, systems, and methods for low power computational imaging
US10001993B2 (en) 2013-08-08 2018-06-19 Linear Algebra Technologies Limited Variable-length instruction buffer management
US9760494B2 (en) 2015-06-24 2017-09-12 International Business Machines Corporation Hybrid tracking of transaction read and write sets
US9858189B2 (en) 2015-06-24 2018-01-02 International Business Machines Corporation Hybrid tracking of transaction read and write sets
US11106466B2 (en) * 2018-06-18 2021-08-31 International Business Machines Corporation Decoupling of conditional branches
CN112181739B (zh) * 2020-09-03 2023-08-08 博流智能科技（南京）有限公司 系统总线测试系统及方法
CN113535499B (zh) * 2021-07-22 2023-10-27 无锡江南计算技术研究所 一种支持多核心共享访问的多类型并存访存流验证方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4084236A (en) * 1977-02-18 1978-04-11 Honeywell Information Systems Inc. Error detection and correction capability for a memory system
US4464717A (en) * 1982-03-31 1984-08-07 Honeywell Information Systems Inc. Multilevel cache system with graceful degradation capability
DE3382152D1 (de) * 1982-12-09 1991-03-07 Sequoia Systems Inc Sicherstellungsspeichersystem.
US4622631B1 (en) * 1983-12-30 1996-04-09 Recognition Int Inc Data processing system having a data coherence solution
JPS6324428A (ja) * 1986-07-17 1988-02-01 Mitsubishi Electric Corp キヤツシユメモリ
US4851993A (en) * 1987-04-20 1989-07-25 Amdahl Corporation Cache move-in bypass
US4831622A (en) * 1987-12-22 1989-05-16 Honeywell Bull Inc. Apparatus for forcing a reload from main memory upon cache memory error
US5072369A (en) * 1989-04-07 1991-12-10 Tektronix, Inc. Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113703365A (zh) * 2021-08-26 2021-11-26 北京无线电测量研究所 设备监测信息的管理方法及系统
CN113703365B (zh) * 2021-08-26 2023-03-21 北京无线电测量研究所 设备监测信息的管理方法及系统

Also Published As

Publication number Publication date
US5155843A (en) 1992-10-13
EP0465319A2 (de) 1992-01-08
DE69111707T2 (de) 1996-03-28
CA2045715A1 (en) 1991-12-30
EP0465319B1 (de) 1995-08-02
EP0465319A3 (en) 1993-02-24
JPH0695964A (ja) 1994-04-08

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