DE69032655D1 - Seitenspeicher-Steuerschaltung - Google Patents

Seitenspeicher-Steuerschaltung

Info

Publication number
DE69032655D1
DE69032655D1 DE69032655T DE69032655T DE69032655D1 DE 69032655 D1 DE69032655 D1 DE 69032655D1 DE 69032655 T DE69032655 T DE 69032655T DE 69032655 T DE69032655 T DE 69032655T DE 69032655 D1 DE69032655 D1 DE 69032655D1
Authority
DE
Germany
Prior art keywords
control circuit
memory control
page memory
page
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69032655T
Other languages
English (en)
Other versions
DE69032655T2 (de
Inventor
David J Mayer
Paul R Culley
Mark E Taylor
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compaq Computer Corp
Original Assignee
Compaq Computer Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compaq Computer Corp filed Critical Compaq Computer Corp
Application granted granted Critical
Publication of DE69032655D1 publication Critical patent/DE69032655D1/de
Publication of DE69032655T2 publication Critical patent/DE69032655T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69032655T 1989-11-03 1990-10-24 Seitenspeicher-Steuerschaltung Expired - Lifetime DE69032655T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US43167089A 1989-11-03 1989-11-03

Publications (2)

Publication Number Publication Date
DE69032655D1 true DE69032655D1 (de) 1998-10-22
DE69032655T2 DE69032655T2 (de) 1999-02-11

Family

ID=23712939

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69032655T Expired - Lifetime DE69032655T2 (de) 1989-11-03 1990-10-24 Seitenspeicher-Steuerschaltung

Country Status (4)

Country Link
US (1) US5303364A (de)
EP (1) EP0427425B1 (de)
CA (1) CA2028085A1 (de)
DE (1) DE69032655T2 (de)

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GB2242294B (en) * 1990-03-19 1993-12-22 Apple Computer Memory architecture using page mode writes and single level write buffering
JPH04270440A (ja) * 1991-02-26 1992-09-25 Fujitsu Ltd アクセス方式
CA2065992A1 (en) * 1991-06-07 1992-12-08 Jorge Eduardo Lenta Personal computer with enhanced memory access and method
JP3259969B2 (ja) * 1991-07-09 2002-02-25 株式会社東芝 キャッシュメモリ制御装置
US5469555A (en) * 1991-12-19 1995-11-21 Opti, Inc. Adaptive write-back method and apparatus wherein the cache system operates in a combination of write-back and write-through modes for a cache-based microprocessor system
US5390308A (en) * 1992-04-15 1995-02-14 Rambus, Inc. Method and apparatus for address mapping of dynamic random access memory
US5537553A (en) * 1992-11-13 1996-07-16 Matsushita Electric Industrial Co., Ltd. Method of and apparatus for bus control and data processor
CA2118662C (en) * 1993-03-22 1999-07-13 Paul A. Santeler Memory controller having all dram address and control signals provided synchronously from a single device
US5651130A (en) * 1993-03-22 1997-07-22 Compaq Computer Corporation Memory controller that dynamically predicts page misses
US5640527A (en) * 1993-07-14 1997-06-17 Dell Usa, L.P. Apparatus and method for address pipelining of dynamic random access memory utilizing transparent page address latches to reduce wait states
US6003120A (en) * 1993-12-30 1999-12-14 Intel Corporation Method and apparatus for performing variable length processor write cycles
US5717894A (en) * 1994-03-07 1998-02-10 Dell Usa, L.P. Method and apparatus for reducing write cycle wait states in a non-zero wait state cache system
JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
US5603007A (en) * 1994-03-14 1997-02-11 Apple Computer, Inc. Methods and apparatus for controlling back-to-back burst reads in a cache system
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US5634112A (en) * 1994-10-14 1997-05-27 Compaq Computer Corporation Memory controller having precharge prediction based on processor and PCI bus cycles
US5701433A (en) * 1994-10-14 1997-12-23 Compaq Computer Corporation Computer system having a memory controller which performs readahead operations which can be aborted prior to completion
AU703750B2 (en) * 1994-10-14 1999-04-01 Compaq Computer Corporation Easily programmable memory controller which can access different speed memory devices on different cycles
US5862389A (en) * 1995-02-27 1999-01-19 Intel Corporation Method and apparatus for selectively invoking a particular interrupt service routine for a particular interrupt request
US5572686A (en) * 1995-06-05 1996-11-05 Apple Computer, Inc. Bus arbitration scheme with priority switching and timer
US5619471A (en) * 1995-06-06 1997-04-08 Apple Computer, Inc. Memory controller for both interleaved and non-interleaved memory
US5737572A (en) * 1995-06-06 1998-04-07 Apple Computer, Inc. Bank selection logic for memory controllers
US5765203A (en) * 1995-12-19 1998-06-09 Seagate Technology, Inc. Storage and addressing method for a buffer memory control system for accessing user and error imformation
US6504548B2 (en) 1998-09-18 2003-01-07 Hitachi, Ltd. Data processing apparatus having DRAM incorporated therein
US6295074B1 (en) 1996-03-21 2001-09-25 Hitachi, Ltd. Data processing apparatus having DRAM incorporated therein
US6014759A (en) 1997-06-13 2000-01-11 Micron Technology, Inc. Method and apparatus for transferring test data from a memory array
US6044429A (en) 1997-07-10 2000-03-28 Micron Technology, Inc. Method and apparatus for collision-free data transfers in a memory device with selectable data or address paths
US6070227A (en) * 1997-10-31 2000-05-30 Hewlett-Packard Company Main memory bank indexing scheme that optimizes consecutive page hits by linking main memory bank address organization to cache memory address organization
US6052756A (en) * 1998-01-23 2000-04-18 Oki Electric Industry Co., Ltd. Memory page management
US6405280B1 (en) 1998-06-05 2002-06-11 Micron Technology, Inc. Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence
US6631474B1 (en) * 1999-12-31 2003-10-07 Intel Corporation System to coordinate switching between first and second processors and to coordinate cache coherency between first and second processors during switching
KR100518576B1 (ko) * 2003-05-24 2005-10-04 삼성전자주식회사 버스 중재기 및 버스 중재방법
US7787324B2 (en) 2006-10-13 2010-08-31 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
US8027218B2 (en) 2006-10-13 2011-09-27 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
US8675442B2 (en) * 2011-10-04 2014-03-18 Qualcomm Incorporated Energy efficient memory with reconfigurable decoding
WO2014193412A1 (en) 2013-05-31 2014-12-04 Hewlett-Packard Development Company, L.P. Memory error determination

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Publication number Priority date Publication date Assignee Title
US4954951A (en) * 1970-12-28 1990-09-04 Hyatt Gilbert P System and method for increasing memory performance
GB2112256B (en) * 1981-11-18 1985-11-06 Texas Instruments Ltd Memory apparatus
US4484308A (en) * 1982-09-23 1984-11-20 Motorola, Inc. Serial data mode circuit for a memory
US4621320A (en) * 1983-10-24 1986-11-04 Sperry Corporation Multi-user read-ahead memory
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
US4899275A (en) * 1985-02-22 1990-02-06 Intergraph Corporation Cache-MMU system
US4785398A (en) * 1985-12-19 1988-11-15 Honeywell Bull Inc. Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
US5005118A (en) * 1987-04-10 1991-04-02 Tandem Computers Incorporated Method and apparatus for modifying micro-instructions using a macro-instruction pipeline
IT1215539B (it) * 1987-06-03 1990-02-14 Honeywell Inf Systems Memoria tampone trasparente.
JPH0194592A (ja) * 1987-10-06 1989-04-13 Fujitsu Ltd 半導体メモリ
US4984209A (en) * 1987-10-30 1991-01-08 Zenith Data Systems Corporation Burst refresh of dynamic random access memory for personal computers
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JPH01146187A (ja) * 1987-12-02 1989-06-08 Mitsubishi Electric Corp キヤッシュメモリ内蔵半導体記憶装置
GB8807849D0 (en) * 1988-04-05 1988-05-05 Int Computers Ltd Data processing apparatus with page mode memory
US5034917A (en) * 1988-05-26 1991-07-23 Bland Patrick M Computer system including a page mode memory with decreased access time and method of operation thereof
US4939641A (en) * 1988-06-30 1990-07-03 Wang Laboratories, Inc. Multi-processor system with cache memories
US4933910A (en) * 1988-07-06 1990-06-12 Zenith Data Systems Corporation Method for improving the page hit ratio of a page mode main memory system
US5019965A (en) * 1989-02-03 1991-05-28 Digital Equipment Corporation Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width
US5065312A (en) * 1989-08-01 1991-11-12 Digital Equipment Corporation Method of converting unique data to system data

Also Published As

Publication number Publication date
CA2028085A1 (en) 1991-05-04
EP0427425A3 (en) 1992-05-27
DE69032655T2 (de) 1999-02-11
EP0427425B1 (de) 1998-09-16
US5303364A (en) 1994-04-12
EP0427425A2 (de) 1991-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition