DE69030945D1 - Zweistufiger Adressübersetzungspufferspeicher mit partiellen Adressen zur Geschwindigkeitserhöhung - Google Patents

Zweistufiger Adressübersetzungspufferspeicher mit partiellen Adressen zur Geschwindigkeitserhöhung

Info

Publication number
DE69030945D1
DE69030945D1 DE69030945T DE69030945T DE69030945D1 DE 69030945 D1 DE69030945 D1 DE 69030945D1 DE 69030945 T DE69030945 T DE 69030945T DE 69030945 T DE69030945 T DE 69030945T DE 69030945 D1 DE69030945 D1 DE 69030945D1
Authority
DE
Germany
Prior art keywords
address translation
increase speed
translation buffer
level address
partial addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69030945T
Other languages
English (en)
Other versions
DE69030945T2 (de
Inventor
George S Taylor
Michael P Farmwald
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MIPS Tech LLC
Original Assignee
Silicon Graphics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Graphics Inc filed Critical Silicon Graphics Inc
Publication of DE69030945D1 publication Critical patent/DE69030945D1/de
Application granted granted Critical
Publication of DE69030945T2 publication Critical patent/DE69030945T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1045—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache
    • G06F12/1054—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] associated with a data cache the data cache being concurrently physically addressed
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/653—Page colouring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE69030945T 1989-12-01 1990-11-29 Zweistufiger Adressübersetzungspufferspeicher mit partiellen Adressen zur Geschwindigkeitserhöhung Expired - Lifetime DE69030945T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/444,594 US5226133A (en) 1989-12-01 1989-12-01 Two-level translation look-aside buffer using partial addresses for enhanced speed

Publications (2)

Publication Number Publication Date
DE69030945D1 true DE69030945D1 (de) 1997-07-24
DE69030945T2 DE69030945T2 (de) 1998-01-29

Family

ID=23765553

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69030945T Expired - Lifetime DE69030945T2 (de) 1989-12-01 1990-11-29 Zweistufiger Adressübersetzungspufferspeicher mit partiellen Adressen zur Geschwindigkeitserhöhung

Country Status (4)

Country Link
US (1) US5226133A (de)
EP (1) EP0431463B1 (de)
JP (1) JPH03266153A (de)
DE (1) DE69030945T2 (de)

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JP3190700B2 (ja) * 1991-05-31 2001-07-23 日本電気株式会社 アドレス変換装置
JP3259969B2 (ja) * 1991-07-09 2002-02-25 株式会社東芝 キャッシュメモリ制御装置
WO1993004431A1 (fr) * 1991-08-15 1993-03-04 Fujitsu Limited Systeme de commande de memoire tampon
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US5450558A (en) * 1992-05-27 1995-09-12 Hewlett-Packard Company System for translating virtual address to real address by duplicating mask information in real page number corresponds to block entry of virtual page number
US5574877A (en) * 1992-09-25 1996-11-12 Silicon Graphics, Inc. TLB with two physical pages per virtual tag
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US5712998A (en) * 1993-07-13 1998-01-27 Intel Corporation Fast fully associative translation lookaside buffer with the ability to store and manage information pertaining to at least two different page sizes
US5848432A (en) * 1993-08-05 1998-12-08 Hitachi, Ltd. Data processor with variable types of cache memories
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US5996062A (en) * 1993-11-24 1999-11-30 Intergraph Corporation Method and apparatus for controlling an instruction pipeline in a data processing system
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US6129458A (en) * 1994-03-23 2000-10-10 At&T Global Information Solutions Company Cache optimization method
JPH09512117A (ja) * 1994-04-15 1997-12-02 ゲーエムデー−フォルシュングスツェントルム インフォルマチオンシュテクニク ゲーエムベーハー データ記憶用キャッシュメモリ装置
WO1995029445A1 (de) * 1994-04-22 1995-11-02 Gmd - Forschungszentrum Informationstechnik Gmbh Cache-speichervorrichtung zum speichern von daten
US5751990A (en) * 1994-04-26 1998-05-12 International Business Machines Corporation Abridged virtual address cache directory
WO1996012231A1 (en) 1994-10-14 1996-04-25 Silicon Graphics, Inc. A translation buffer for detecting and preventing conflicting virtual addresses from being stored therein
US5659697A (en) * 1994-12-14 1997-08-19 International Business Machines Corporation Translation lookaside buffer for faster processing in response to availability of a first virtual address portion before a second virtual address portion
US6006312A (en) * 1995-02-27 1999-12-21 Sun Microsystems, Inc. Cachability attributes of virtual addresses for optimizing performance of virtually and physically indexed caches in maintaining multiply aliased physical addresses
US6029224A (en) * 1995-06-07 2000-02-22 Lucent Technologies Inc. Self-contained memory apparatus having diverse types of memory and distributed control
US5924125A (en) * 1995-08-01 1999-07-13 Arya; Siamak Method and apparatus for parallel access to consecutive TLB entries
US6101590A (en) * 1995-10-10 2000-08-08 Micro Unity Systems Engineering, Inc. Virtual memory system with local and global virtual address translation
US6026476A (en) * 1996-03-19 2000-02-15 Intel Corporation Fast fully associative translation lookaside buffer
US5809562A (en) * 1996-05-20 1998-09-15 Integrated Device Technology, Inc. Cache array select logic allowing cache array size to differ from physical page size
US5928352A (en) * 1996-09-16 1999-07-27 Intel Corporation Method and apparatus for implementing a fully-associative translation look-aside buffer having a variable numbers of bits representing a virtual address entry
US5946718A (en) * 1997-05-30 1999-08-31 National Semiconductor Corporation Shadow translation look-aside buffer and method of operation
US6065091A (en) * 1997-05-30 2000-05-16 Via-Cyrix, Inc. Translation look-aside buffer slice circuit and method of operation
US6049855A (en) * 1997-07-02 2000-04-11 Micron Electronics, Inc. Segmented memory system employing different interleaving scheme for each different memory segment
US6079003A (en) 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Reverse TLB for providing branch target address in a microprocessor having a physically-tagged cache
US6079005A (en) * 1997-11-20 2000-06-20 Advanced Micro Devices, Inc. Microprocessor including virtual address branch prediction and current page register to provide page portion of virtual and physical fetch address
US6356996B1 (en) * 1998-03-24 2002-03-12 Novell, Inc. Cache fencing for interpretive environments
US6564311B2 (en) * 1999-01-19 2003-05-13 Matsushita Electric Industrial Co., Ltd. Apparatus for translation between virtual and physical addresses using a virtual page number, a physical page number, a process identifier and a global bit
US6469705B1 (en) * 1999-09-21 2002-10-22 Autodesk Canada Inc. Cache addressing
US6604187B1 (en) * 2000-06-19 2003-08-05 Advanced Micro Devices, Inc. Providing global translations with address space numbers
EP1213650A3 (de) * 2000-08-21 2006-08-30 Texas Instruments France Auf aktueller Aufgabe basierte Prioritätsarbitrierung und Speicherverwaltungseinheit
US20020144078A1 (en) * 2001-03-30 2002-10-03 Siroyan Limited Address translation
GB2373889A (en) * 2001-03-30 2002-10-02 Siroyan Ltd Address translation with partial physical addresses
KR100389867B1 (ko) * 2001-06-04 2003-07-04 삼성전자주식회사 플래시 메모리 관리방법
US20030163643A1 (en) * 2002-02-22 2003-08-28 Riedlinger Reid James Bank conflict determination
US6920693B2 (en) * 2002-07-24 2005-07-26 L&L Products, Inc. Dynamic self-adjusting assembly for sealing, baffling or structural reinforcement
JP2004164395A (ja) * 2002-11-14 2004-06-10 Renesas Technology Corp アドレス変換装置
US7117290B2 (en) * 2003-09-03 2006-10-03 Advanced Micro Devices, Inc. MicroTLB and micro tag for reducing power in a processor
US20050182903A1 (en) * 2004-02-12 2005-08-18 Mips Technologies, Inc. Apparatus and method for preventing duplicate matching entries in a translation lookaside buffer
US7558939B2 (en) * 2005-03-08 2009-07-07 Mips Technologies, Inc. Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor
EP1717708B1 (de) 2005-04-29 2010-09-01 STMicroelectronics Srl Ein verbessertes Cache-Speicher System
US9075733B1 (en) * 2010-05-20 2015-07-07 Seagate Technology Llc Selective storage of address mapping metadata in a system having multiple memories
US10372618B2 (en) * 2016-10-14 2019-08-06 Arm Limited Apparatus and method for maintaining address translation data within an address translation cache

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US4170039A (en) * 1978-07-17 1979-10-02 International Business Machines Corporation Virtual address translation speed up technique
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US4493026A (en) * 1982-05-26 1985-01-08 International Business Machines Corporation Set associative sector cache
US4602368A (en) * 1983-04-15 1986-07-22 Honeywell Information Systems Inc. Dual validity bit arrays
US4682281A (en) * 1983-08-30 1987-07-21 Amdahl Corporation Data storage unit employing translation lookaside buffer pointer
US4991081A (en) * 1984-10-31 1991-02-05 Texas Instruments Incorporated Cache memory addressable by both physical and virtual addresses
US4737909A (en) * 1985-04-01 1988-04-12 National Semiconductor Corp. Cache memory address apparatus
US4763244A (en) * 1986-01-15 1988-08-09 Motorola, Inc. Paged memory management unit capable of selectively supporting multiple address spaces
US4914582A (en) * 1986-06-27 1990-04-03 Hewlett-Packard Company Cache tag lookaside
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US4969122A (en) * 1989-08-21 1990-11-06 Sun Microsystems, Inc. Apparatus for page tagging in a computer system

Also Published As

Publication number Publication date
US5226133A (en) 1993-07-06
EP0431463A3 (en) 1992-03-18
EP0431463B1 (de) 1997-06-18
DE69030945T2 (de) 1998-01-29
EP0431463A2 (de) 1991-06-12
JPH03266153A (ja) 1991-11-27

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MIPS TECHNOLOGIES,INC., MOUNTAIN VIEW,CALIF.,, US