DE69020772D1 - Wannen-Bildung für Halbleiter-Bauelemente. - Google Patents
Wannen-Bildung für Halbleiter-Bauelemente.Info
- Publication number
- DE69020772D1 DE69020772D1 DE69020772T DE69020772T DE69020772D1 DE 69020772 D1 DE69020772 D1 DE 69020772D1 DE 69020772 T DE69020772 T DE 69020772T DE 69020772 T DE69020772 T DE 69020772T DE 69020772 D1 DE69020772 D1 DE 69020772D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor components
- trough formation
- trough
- formation
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
- H01L21/31654—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself
- H01L21/31658—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe
- H01L21/31662—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of semiconductor materials, e.g. the body itself by thermal oxidation, e.g. of SiGe of silicon in uncombined form
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/07—Guard rings and cmos
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB898907897A GB8907897D0 (en) | 1989-04-07 | 1989-04-07 | Forming wells in semiconductor devices |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69020772D1 true DE69020772D1 (de) | 1995-08-17 |
DE69020772T2 DE69020772T2 (de) | 1995-12-21 |
Family
ID=10654649
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69020772T Expired - Fee Related DE69020772T2 (de) | 1989-04-07 | 1990-03-16 | Wannen-Bildung für Halbleiter-Bauelemente. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5045495A (de) |
EP (1) | EP0391561B1 (de) |
JP (1) | JPH02288359A (de) |
DE (1) | DE69020772T2 (de) |
GB (1) | GB8907897D0 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05271928A (ja) * | 1992-03-23 | 1993-10-19 | Hitachi Ltd | 摺動部材とその製法並びにその用途 |
US5300797A (en) * | 1992-03-31 | 1994-04-05 | Sgs-Thomson Microelectronics, Inc. | Coplanar twin-well integrated circuit structure |
EP0605965A3 (de) * | 1992-12-31 | 1994-11-02 | At & T Corp | Verfahren zur Herstellung CMOS-integrierter Schaltungen. |
EP0716443B1 (de) * | 1994-12-08 | 2000-10-11 | AT&T Corp. | Fabrikation einer integrierten Schaltung mit Zwillingswannen |
KR0146080B1 (ko) * | 1995-07-26 | 1998-08-01 | 문정환 | 반도체 소자의 트윈 웰 형성방법 |
US5946564A (en) * | 1997-08-04 | 1999-08-31 | Micron Technology, Inc. | Methods of forming integrated circuitry and integrated circuitry |
KR100620218B1 (ko) * | 2003-12-31 | 2006-09-11 | 동부일렉트로닉스 주식회사 | 반도체 소자 |
KR100734325B1 (ko) * | 2006-07-14 | 2007-07-02 | 삼성전자주식회사 | 반도체 소자의 제조방법 |
KR101008656B1 (ko) * | 2008-05-22 | 2011-01-25 | 한국표준과학연구원 | 2차원 도펀트이미징 공간분해능 기준 물질 |
US8153496B1 (en) * | 2011-03-07 | 2012-04-10 | Varian Semiconductor Equipment Associates, Inc. | Self-aligned process and method for fabrication of high efficiency solar cells |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4027380A (en) * | 1974-06-03 | 1977-06-07 | Fairchild Camera And Instrument Corporation | Complementary insulated gate field effect transistor structure and process for fabricating the structure |
US4442591A (en) * | 1982-02-01 | 1984-04-17 | Texas Instruments Incorporated | High-voltage CMOS process |
US4435895A (en) * | 1982-04-05 | 1984-03-13 | Bell Telephone Laboratories, Incorporated | Process for forming complementary integrated circuit devices |
DE3314450A1 (de) * | 1983-04-21 | 1984-10-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4516316A (en) * | 1984-03-27 | 1985-05-14 | Advanced Micro Devices, Inc. | Method of making improved twin wells for CMOS devices by controlling spatial separation |
US4554726A (en) * | 1984-04-17 | 1985-11-26 | At&T Bell Laboratories | CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well |
US4925806A (en) * | 1988-03-17 | 1990-05-15 | Northern Telecom Limited | Method for making a doped well in a semiconductor substrate |
-
1989
- 1989-04-07 GB GB898907897A patent/GB8907897D0/en active Pending
-
1990
- 1990-03-16 DE DE69020772T patent/DE69020772T2/de not_active Expired - Fee Related
- 1990-03-16 EP EP90302868A patent/EP0391561B1/de not_active Expired - Lifetime
- 1990-03-30 US US07/502,532 patent/US5045495A/en not_active Expired - Lifetime
- 1990-04-03 JP JP2089011A patent/JPH02288359A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
GB8907897D0 (en) | 1989-05-24 |
US5045495A (en) | 1991-09-03 |
EP0391561B1 (de) | 1995-07-12 |
EP0391561A3 (de) | 1992-01-02 |
JPH02288359A (ja) | 1990-11-28 |
EP0391561A2 (de) | 1990-10-10 |
DE69020772T2 (de) | 1995-12-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SGS-THOMSON MICROELECTRONICS LTD., MARLOW, BUCKING |
|
8339 | Ceased/non-payment of the annual fee |