DE68923571D1 - Dynamischer RAM-Speicher mit Redundanz und verbesserter Prüfbarkeit. - Google Patents

Dynamischer RAM-Speicher mit Redundanz und verbesserter Prüfbarkeit.

Info

Publication number
DE68923571D1
DE68923571D1 DE68923571T DE68923571T DE68923571D1 DE 68923571 D1 DE68923571 D1 DE 68923571D1 DE 68923571 T DE68923571 T DE 68923571T DE 68923571 T DE68923571 T DE 68923571T DE 68923571 D1 DE68923571 D1 DE 68923571D1
Authority
DE
Germany
Prior art keywords
redundancy
dynamic ram
improved testability
testability
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923571T
Other languages
English (en)
Other versions
DE68923571T2 (de
Inventor
Richard D Crisp
George Greg Watkins
George P Hoekstra
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE68923571D1 publication Critical patent/DE68923571D1/de
Publication of DE68923571T2 publication Critical patent/DE68923571T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE68923571T 1988-03-24 1989-03-02 Dynamischer RAM-Speicher mit Redundanz und verbesserter Prüfbarkeit. Expired - Fee Related DE68923571T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/172,514 US4866676A (en) 1988-03-24 1988-03-24 Testing arrangement for a DRAM with redundancy

Publications (2)

Publication Number Publication Date
DE68923571D1 true DE68923571D1 (de) 1995-08-31
DE68923571T2 DE68923571T2 (de) 1996-04-11

Family

ID=22628028

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923571T Expired - Fee Related DE68923571T2 (de) 1988-03-24 1989-03-02 Dynamischer RAM-Speicher mit Redundanz und verbesserter Prüfbarkeit.

Country Status (5)

Country Link
US (1) US4866676A (de)
EP (1) EP0335125B1 (de)
JP (1) JP2782764B2 (de)
KR (1) KR890015132A (de)
DE (1) DE68923571T2 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5426607A (en) * 1988-04-27 1995-06-20 Sharp Kabushiki Kaisha Redundant circuit for memory having redundant block operatively connected to special one of normal blocks
US5208778A (en) * 1988-11-16 1993-05-04 Mitsubishi Denki Kabushiki Kaisha Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof
US5136543A (en) * 1989-05-12 1992-08-04 Mitsubishi Denki Kabushiki Kaisha Data descrambling in semiconductor memory device
JPH03162800A (ja) * 1989-08-29 1991-07-12 Mitsubishi Electric Corp 半導体メモリ装置
JP2915945B2 (ja) * 1990-01-12 1999-07-05 株式会社アドバンテスト メモリ試験装置
JP2982920B2 (ja) * 1990-07-10 1999-11-29 三菱電機株式会社 半導体記憶装置
JP2863012B2 (ja) * 1990-12-18 1999-03-03 三菱電機株式会社 半導体記憶装置
KR960007478B1 (ko) * 1990-12-27 1996-06-03 가부시키가이샤 도시바 반도체장치 및 반도체장치의 제조방법
KR940008211B1 (ko) * 1991-08-21 1994-09-08 삼성전자 주식회사 반도체메모리장치의 리던던트 셀 어레이 배열방법
US5343429A (en) * 1991-12-06 1994-08-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having redundant circuit and method of testing to see whether or not redundant circuit is used therein
JP3215566B2 (ja) * 1994-01-31 2001-10-09 富士通株式会社 半導体記憶装置
US5555212A (en) * 1994-09-19 1996-09-10 Kabushiki Kaisha Toshiba Method and apparatus for redundancy word line replacement in a semiconductor memory device
US5546349A (en) * 1995-03-13 1996-08-13 Kabushiki Kaisha Toshiba Exchangeable hierarchical data line structure
US6058052A (en) * 1997-08-21 2000-05-02 Cypress Semiconductor Corp. Redundancy scheme providing improvements in redundant circuit access time and integrated circuit layout area
KR100252053B1 (ko) * 1997-12-04 2000-05-01 윤종용 칼럼 방향의 데이터 입출력선을 가지는 반도체메모리장치와불량셀 구제회로 및 방법
US5907511A (en) * 1997-12-23 1999-05-25 Lsi Logic Corporation Electrically selectable redundant components for an embedded DRAM
US5901095A (en) * 1997-12-23 1999-05-04 Lsi Logic Corporation Reprogrammable address selector for an embedded DRAM
US5896331A (en) * 1997-12-23 1999-04-20 Lsi Logic Corporation Reprogrammable addressing process for embedded DRAM
US6064588A (en) * 1998-03-30 2000-05-16 Lsi Logic Corporation Embedded dram with noise-protected differential capacitor memory cells
US5999440A (en) * 1998-03-30 1999-12-07 Lsi Logic Corporation Embedded DRAM with noise-protecting substrate isolation well
US5978304A (en) * 1998-06-30 1999-11-02 Lsi Logic Corporation Hierarchical, adaptable-configuration dynamic random access memory
US6005824A (en) * 1998-06-30 1999-12-21 Lsi Logic Corporation Inherently compensated clocking circuit for dynamic random access memory
JP3741258B2 (ja) * 2000-03-31 2006-02-01 シャープ株式会社 半導体記憶装置およびその救済方法
US6675272B2 (en) 2001-04-24 2004-01-06 Rambus Inc. Method and apparatus for coordinating memory operations among diversely-located memory components
US8391039B2 (en) 2001-04-24 2013-03-05 Rambus Inc. Memory module with termination component
US7301831B2 (en) 2004-09-15 2007-11-27 Rambus Inc. Memory systems with variable delays for write data signals

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3753244A (en) * 1971-08-18 1973-08-14 Ibm Yield enhancement redundancy technique
US4494220A (en) * 1982-11-24 1985-01-15 At&T Bell Laboratories Folded bit line memory with one decoder per pair of spare rows
JPS60205895A (ja) * 1984-03-30 1985-10-17 Fujitsu Ltd 半導体記憶装置
US4757474A (en) * 1986-01-28 1988-07-12 Fujitsu Limited Semiconductor memory device having redundancy circuit portion

Also Published As

Publication number Publication date
EP0335125B1 (de) 1995-07-26
US4866676A (en) 1989-09-12
DE68923571T2 (de) 1996-04-11
EP0335125A2 (de) 1989-10-04
JPH0210600A (ja) 1990-01-16
EP0335125A3 (de) 1991-06-19
JP2782764B2 (ja) 1998-08-06
KR890015132A (ko) 1989-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee