DE60329076D1 - Crossbar-einrichtung mit verringerter parasitärer kapazitätslast - Google Patents

Crossbar-einrichtung mit verringerter parasitärer kapazitätslast

Info

Publication number
DE60329076D1
DE60329076D1 DE60329076T DE60329076T DE60329076D1 DE 60329076 D1 DE60329076 D1 DE 60329076D1 DE 60329076 T DE60329076 T DE 60329076T DE 60329076 T DE60329076 T DE 60329076T DE 60329076 D1 DE60329076 D1 DE 60329076D1
Authority
DE
Germany
Prior art keywords
crossbar
lines
output buffers
reduced parasitic
crossbar device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60329076T
Other languages
English (en)
Inventor
Frederic Reblewski
Olivier Lepape
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Abound Logic SAS
Original Assignee
2000 PARC BUROSPACE BIEVRES M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 2000 PARC BUROSPACE BIEVRES M filed Critical 2000 PARC BUROSPACE BIEVRES M
Application granted granted Critical
Publication of DE60329076D1 publication Critical patent/DE60329076D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/693—Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents
    • H03K17/161—Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162—Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit

Landscapes

  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Breakers (AREA)
DE60329076T 2002-01-10 2003-01-07 Crossbar-einrichtung mit verringerter parasitärer kapazitätslast Expired - Lifetime DE60329076D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/043,964 US6874136B2 (en) 2002-01-10 2002-01-10 Crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits
PCT/EP2003/000063 WO2003058816A1 (en) 2002-01-10 2003-01-07 A crossbar device with reduced parasitic capacitive loading and usage of crossbar devices in reconfigurable circuits

Publications (1)

Publication Number Publication Date
DE60329076D1 true DE60329076D1 (de) 2009-10-15

Family

ID=21929828

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60329076T Expired - Lifetime DE60329076D1 (de) 2002-01-10 2003-01-07 Crossbar-einrichtung mit verringerter parasitärer kapazitätslast

Country Status (8)

Country Link
US (1) US6874136B2 (de)
EP (2) EP1472787B1 (de)
JP (2) JP2006502603A (de)
AT (1) ATE441975T1 (de)
AU (1) AU2003235769A1 (de)
CA (1) CA2473031C (de)
DE (1) DE60329076D1 (de)
WO (1) WO2003058816A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6993622B2 (en) * 2001-10-31 2006-01-31 Netlogic Microsystems, Inc. Bit level programming interface in a content addressable memory
US7210003B2 (en) * 2001-10-31 2007-04-24 Netlogic Microsystems, Inc. Comparand generation in a content addressable memory
US7237058B2 (en) * 2002-01-14 2007-06-26 Netlogic Microsystems, Inc. Input data selection for content addressable memory
US20060018142A1 (en) * 2003-08-11 2006-01-26 Varadarajan Srinivasan Concurrent searching of different tables within a content addressable memory
JP2009539444A (ja) * 2006-06-06 2009-11-19 ノボ・ノルデイスク・エー／エス 皮膚に取付け可能な装置及び同装置のパッケージを含むアセンブリ
US8245177B2 (en) * 2008-10-30 2012-08-14 Meta Systems Crossbar structure with mechanism for generating constant outputs
WO2010144092A1 (en) * 2009-06-12 2010-12-16 Hewlett-Packard Development Company, L.P. Capacitive crossbar arrays

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4056807A (en) * 1976-08-16 1977-11-01 Bell Telephone Laboratories, Incorporated Electronically alterable diode logic circuit
DE3151080C2 (de) * 1981-12-23 1988-12-01 Felten & Guilleaume Fernmeldeanlagen GmbH, 8500 Nürnberg Koppelfeldeinrichtung
US5151623A (en) * 1985-03-29 1992-09-29 Advanced Micro Devices, Inc. Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix
LU86788A1 (de) * 1986-06-19 1987-07-24 Siemens Ag Breitbandsignal-koppeleinrichtung
US5644496A (en) * 1989-08-15 1997-07-01 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5298805A (en) * 1991-08-29 1994-03-29 National Semiconductor Corporation Versatile and efficient cell-to-local bus interface in a configurable logic array
US5260610A (en) 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
DE69223772D1 (de) 1991-12-26 1998-02-05 Altera Corp Eprom-basierte kreuzschienenschalter mit nullruheleistungsaufnahme
WO1995022205A1 (en) * 1994-02-15 1995-08-17 Xilinx, Inc. Tile based architecture for fpga
GB2300085A (en) 1995-04-18 1996-10-23 Northern Telecom Ltd A high speed switch
US5717871A (en) * 1995-08-17 1998-02-10 I-Cube, Inc. Crossbar switch with input/output buffers having multiplexed control inputs
US5744990A (en) * 1995-11-08 1998-04-28 Standard Microsystems Corporation Enhanced power-on-reset/low voltage detection circuit
US6175952B1 (en) * 1997-05-27 2001-01-16 Altera Corporation Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions
US5886943A (en) * 1996-09-18 1999-03-23 Hitachi, Ltd. Semiconductor memory having a hierarchical data line structure
US6289494B1 (en) * 1997-11-12 2001-09-11 Quickturn Design Systems, Inc. Optimized emulation and prototyping architecture
KR100631909B1 (ko) * 1999-12-13 2006-10-04 삼성전자주식회사 버퍼회로

Also Published As

Publication number Publication date
ATE441975T1 (de) 2009-09-15
JP2006502603A (ja) 2006-01-19
EP2110948A1 (de) 2009-10-21
EP1472787B1 (de) 2009-09-02
US6874136B2 (en) 2005-03-29
WO2003058816A1 (en) 2003-07-17
EP1472787A1 (de) 2004-11-03
CA2473031A1 (en) 2003-07-17
JP2010063127A (ja) 2010-03-18
AU2003235769A1 (en) 2003-07-24
CA2473031C (en) 2009-12-01
US20030131331A1 (en) 2003-07-10

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: ABOUND LOGIC S.A.S., BIEVRES, FR

8364 No opposition during term of opposition