DE60329069D1 - Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht-lehrlaufrückkehr von adressen- und steuersignalen - Google Patents

Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht-lehrlaufrückkehr von adressen- und steuersignalen

Info

Publication number
DE60329069D1
DE60329069D1 DE60329069T DE60329069T DE60329069D1 DE 60329069 D1 DE60329069 D1 DE 60329069D1 DE 60329069 T DE60329069 T DE 60329069T DE 60329069 T DE60329069 T DE 60329069T DE 60329069 D1 DE60329069 D1 DE 60329069D1
Authority
DE
Germany
Prior art keywords
address
control signals
return
power reduction
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60329069T
Other languages
English (en)
Inventor
Jeffrey Wilcox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of DE60329069D1 publication Critical patent/DE60329069D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Selective Calling Equipment (AREA)
  • Programmable Controllers (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
DE60329069T 2002-01-08 2003-01-03 Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht-lehrlaufrückkehr von adressen- und steuersignalen Expired - Lifetime DE60329069D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/042,862 US6529442B1 (en) 2002-01-08 2002-01-08 Memory controller with AC power reduction through non-return-to-idle of address and control signals
PCT/US2003/000164 WO2003058629A1 (en) 2002-01-08 2003-01-03 Memory controller with ac power reduction through non-return-to-idle of address and control signals

Publications (1)

Publication Number Publication Date
DE60329069D1 true DE60329069D1 (de) 2009-10-15

Family

ID=21924131

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60329069T Expired - Lifetime DE60329069D1 (de) 2002-01-08 2003-01-03 Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht-lehrlaufrückkehr von adressen- und steuersignalen

Country Status (9)

Country Link
US (1) US6529442B1 (de)
EP (1) EP1464056B1 (de)
KR (1) KR100647169B1 (de)
CN (1) CN1613115B (de)
AT (1) ATE441926T1 (de)
AU (1) AU2003202883A1 (de)
DE (1) DE60329069D1 (de)
TW (1) TWI229794B (de)
WO (1) WO2003058629A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060080461A1 (en) * 2004-06-02 2006-04-13 Wilcox Jeffrey R Packet exchange for controlling system power modes
KR100735749B1 (ko) * 2005-11-28 2007-07-06 삼성전자주식회사 반도체 메모리 장치, 메모리 시스템, 및 데이터 송수신시스템
DE102006004346A1 (de) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Datenbusschnittstelle mit abschaltbarem Takt
US8266393B2 (en) * 2008-06-04 2012-09-11 Microsoft Corporation Coordination among multiple memory controllers
KR20190012571A (ko) * 2017-07-27 2019-02-11 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
CN111290977B (zh) * 2020-01-16 2021-11-16 芯创智（北京）微电子有限公司 一种基于ddr多数据单元的寄存器访问系统及方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461266A (en) * 1990-11-27 1995-10-24 Hitachi, Ltd. Power consumption control system
US5473572A (en) 1993-02-16 1995-12-05 Chips And Technologies, Inc. Power saving system for a memory controller
US5848022A (en) 1997-05-02 1998-12-08 Integrated Silicon Solution Inc. Address enable circuit in synchronous SRAM
US6233661B1 (en) 1998-04-28 2001-05-15 Compaq Computer Corporation Computer system with memory controller that hides the next cycle during the current cycle
US6269433B1 (en) 1998-04-29 2001-07-31 Compaq Computer Corporation Memory controller using queue look-ahead to reduce memory latency
US6111812A (en) 1999-07-23 2000-08-29 Micron Technology, Inc. Method and apparatus for adjusting control signal timing in a memory device

Also Published As

Publication number Publication date
TW200301860A (en) 2003-07-16
CN1613115B (zh) 2010-06-16
KR100647169B1 (ko) 2006-11-23
TWI229794B (en) 2005-03-21
EP1464056B1 (de) 2009-09-02
EP1464056A1 (de) 2004-10-06
ATE441926T1 (de) 2009-09-15
CN1613115A (zh) 2005-05-04
WO2003058629A1 (en) 2003-07-17
US6529442B1 (en) 2003-03-04
AU2003202883A1 (en) 2003-07-24
KR20040075064A (ko) 2004-08-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition