ATE441926T1 - Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht- lehrlaufrückkehr von adressen- und steuersignalen - Google Patents

Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht- lehrlaufrückkehr von adressen- und steuersignalen

Info

Publication number
ATE441926T1
ATE441926T1 AT03701995T AT03701995T ATE441926T1 AT E441926 T1 ATE441926 T1 AT E441926T1 AT 03701995 T AT03701995 T AT 03701995T AT 03701995 T AT03701995 T AT 03701995T AT E441926 T1 ATE441926 T1 AT E441926T1
Authority
AT
Austria
Prior art keywords
address
control signals
teaching
return
current consumption
Prior art date
Application number
AT03701995T
Other languages
English (en)
Inventor
Jeffrey Wilcox
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE441926T1 publication Critical patent/ATE441926T1/de

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Selective Calling Equipment (AREA)
  • Programmable Controllers (AREA)
  • Remote Monitoring And Control Of Power-Distribution Networks (AREA)
AT03701995T 2002-01-08 2003-01-03 Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht- lehrlaufrückkehr von adressen- und steuersignalen ATE441926T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/042,862 US6529442B1 (en) 2002-01-08 2002-01-08 Memory controller with AC power reduction through non-return-to-idle of address and control signals
PCT/US2003/000164 WO2003058629A1 (en) 2002-01-08 2003-01-03 Memory controller with ac power reduction through non-return-to-idle of address and control signals

Publications (1)

Publication Number Publication Date
ATE441926T1 true ATE441926T1 (de) 2009-09-15

Family

ID=21924131

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03701995T ATE441926T1 (de) 2002-01-08 2003-01-03 Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht- lehrlaufrückkehr von adressen- und steuersignalen

Country Status (9)

Country Link
US (1) US6529442B1 (de)
EP (1) EP1464056B1 (de)
KR (1) KR100647169B1 (de)
CN (1) CN1613115B (de)
AT (1) ATE441926T1 (de)
AU (1) AU2003202883A1 (de)
DE (1) DE60329069D1 (de)
TW (1) TWI229794B (de)
WO (1) WO2003058629A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060080461A1 (en) * 2004-06-02 2006-04-13 Wilcox Jeffrey R Packet exchange for controlling system power modes
KR100735749B1 (ko) * 2005-11-28 2007-07-06 삼성전자주식회사 반도체 메모리 장치, 메모리 시스템, 및 데이터 송수신시스템
DE102006004346A1 (de) * 2006-01-30 2007-10-18 Deutsche Thomson-Brandt Gmbh Datenbusschnittstelle mit abschaltbarem Takt
US8266393B2 (en) * 2008-06-04 2012-09-11 Microsoft Corporation Coordination among multiple memory controllers
KR20190012571A (ko) * 2017-07-27 2019-02-11 에스케이하이닉스 주식회사 메모리 장치 및 그 동작 방법
CN111290977B (zh) * 2020-01-16 2021-11-16 芯创智（北京）微电子有限公司 一种基于ddr多数据单元的寄存器访问系统及方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5461266A (en) * 1990-11-27 1995-10-24 Hitachi, Ltd. Power consumption control system
US5473572A (en) 1993-02-16 1995-12-05 Chips And Technologies, Inc. Power saving system for a memory controller
US5848022A (en) 1997-05-02 1998-12-08 Integrated Silicon Solution Inc. Address enable circuit in synchronous SRAM
US6233661B1 (en) 1998-04-28 2001-05-15 Compaq Computer Corporation Computer system with memory controller that hides the next cycle during the current cycle
US6269433B1 (en) 1998-04-29 2001-07-31 Compaq Computer Corporation Memory controller using queue look-ahead to reduce memory latency
US6111812A (en) 1999-07-23 2000-08-29 Micron Technology, Inc. Method and apparatus for adjusting control signal timing in a memory device

Also Published As

Publication number Publication date
CN1613115B (zh) 2010-06-16
KR20040075064A (ko) 2004-08-26
TW200301860A (en) 2003-07-16
WO2003058629A1 (en) 2003-07-17
EP1464056B1 (de) 2009-09-02
TWI229794B (en) 2005-03-21
US6529442B1 (en) 2003-03-04
EP1464056A1 (de) 2004-10-06
AU2003202883A1 (en) 2003-07-24
KR100647169B1 (ko) 2006-11-23
CN1613115A (zh) 2005-05-04
DE60329069D1 (de) 2009-10-15

Similar Documents

Publication Publication Date Title
ATE451644T1 (de) Speichersteuerung, die prozessorenergiezustände berücksichtigt
DE602005015225D1 (de) Speicherbefehlsverzögerungsausgleich in einer verketteten speichertopologie
ATE377794T1 (de) Speicherschaltung mit nichtflüchtigem ram und ram
TW368653B (en) Synchronized semiconductor memory device for reducing the power consumption during standby
AR041848A1 (es) Dispositivo y procedimiento para el mantenimiento remoto y el control de una instalacion de ascensor
ATE370546T1 (de) Abwärtsregler mit doppelantrieb
TW200634502A (en) Semiconductor device with a power down mode
TW200627770A (en) Multiphase DC-DC converter
WO2003046990A3 (en) Method and apparatus for standby power reduction in semiconductor devices
KR960035624A (ko) 본딩옵션용 워드라인전압 승압회로 및 그 방법
TWI266335B (en) Local input/output line precharge circuit of semiconductor memory device
JP6297536B2 (ja) Ｄｄｒターミネーションをサポートするための追跡を有する負荷スイッチコントローラのための方法および装置
ATE441926T1 (de) Speichersteuerung mit wechselstromaufnahmeverringerung durch nicht- lehrlaufrückkehr von adressen- und steuersignalen
TW200715302A (en) Clock control circuit for reducing consumption current in data input and output operations and semiconductor memory device including the same and data input and output operations methods of semiconductor memory device
DE602004001684D1 (de) Verfahren und system zum leistungsersparnis in einem sender und sender
KR20100064902A (ko) 버퍼인에이블신호 생성회로 및 이를 이용한 입력회로
TW200636742A (en) Sense amplifier overdriving circuit and semiconductor device using the same
TW200721193A (en) Memory device input buffer, related memory device, controller and system
ATE354209T1 (de) Integrierte schaltung und batteriebetriebenes elektronisches gerät
DE60139490D1 (de) Ausgangstreiber mit gesteuerter Anstiegszeit
ATE403929T1 (de) Steuerungseinrichtung mit umschaltbarer charakteristik
DE602005026936D1 (de) Hochstrom-ladungspumpe für intelligenten leistungsschaltertreiber
TW200623116A (en) Method of controlling mode register set operation in memory device and circuit thereof
JP7370013B2 (ja) 負荷制御システム
JP2008067485A (ja) 電源入力レベル切替回路及び携帯端末

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties