DE60321135D1 - Gegenüber grossen spannungsauslenkungen beständige eingangsstufe - Google Patents

Gegenüber grossen spannungsauslenkungen beständige eingangsstufe

Info

Publication number
DE60321135D1
DE60321135D1 DE60321135T DE60321135T DE60321135D1 DE 60321135 D1 DE60321135 D1 DE 60321135D1 DE 60321135 T DE60321135 T DE 60321135T DE 60321135 T DE60321135 T DE 60321135T DE 60321135 D1 DE60321135 D1 DE 60321135D1
Authority
DE
Germany
Prior art keywords
input
voltage
signal
input stage
iinv
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60321135T
Other languages
English (en)
Inventor
Rolf F P Becker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60321135D1 publication Critical patent/DE60321135D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
DE60321135T 2002-02-06 2003-01-29 Gegenüber grossen spannungsauslenkungen beständige eingangsstufe Expired - Lifetime DE60321135D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02002681 2002-02-06
PCT/IB2003/000298 WO2003067761A1 (en) 2002-02-06 2003-01-29 Input stage resistant against high voltage swings

Publications (1)

Publication Number Publication Date
DE60321135D1 true DE60321135D1 (de) 2008-07-03

Family

ID=27675604

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60321135T Expired - Lifetime DE60321135D1 (de) 2002-02-06 2003-01-29 Gegenüber grossen spannungsauslenkungen beständige eingangsstufe

Country Status (8)

Country Link
US (1) US7135908B2 (de)
EP (1) EP1474870B1 (de)
JP (1) JP2006500795A (de)
CN (1) CN100379152C (de)
AT (1) ATE396540T1 (de)
AU (1) AU2003244420A1 (de)
DE (1) DE60321135D1 (de)
WO (1) WO2003067761A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005122373A1 (ja) * 2004-06-09 2005-12-22 Rohm Co., Ltd レベルシフト回路及びこれを備えたスイッチングレギュレータ
JP2006294903A (ja) * 2005-04-12 2006-10-26 Nec Electronics Corp ヒューズトリミング回路
US7826187B2 (en) * 2008-04-23 2010-11-02 Himax Technologies Limited Transient detection circuit
CN111276956B (zh) * 2020-02-14 2022-05-31 西安微电子技术研究所 一种双极型轨对轨运放输入端通用静电保护电路

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0748652B2 (ja) * 1987-07-23 1995-05-24 三菱電機株式会社 半導体回路装置の入力保護装置
JPH088391A (ja) * 1994-06-17 1996-01-12 Mitsubishi Electric Corp 半導体回路
US5852540A (en) * 1997-09-24 1998-12-22 Intel Corporation Circuit for protecting the input/output stage of a low voltage integrated circuit device from a failure of the internal voltage supply or a difference in the power-up sequencing of supply voltage levels
US6291288B1 (en) * 1999-04-15 2001-09-18 United Microelectronics Corp. Method of fabricating a thin and structurally-undefective dielectric structure for a storage capacitor in dynamic random-access memory
US6181193B1 (en) * 1999-10-08 2001-01-30 International Business Machines Corporation Using thick-oxide CMOS devices to interface high voltage integrated circuits

Also Published As

Publication number Publication date
AU2003244420A1 (en) 2003-09-02
JP2006500795A (ja) 2006-01-05
EP1474870B1 (de) 2008-05-21
WO2003067761A1 (en) 2003-08-14
US20050088208A1 (en) 2005-04-28
US7135908B2 (en) 2006-11-14
EP1474870A1 (de) 2004-11-10
ATE396540T1 (de) 2008-06-15
CN100379152C (zh) 2008-04-02
CN1628416A (zh) 2005-06-15

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: RICHTER, WERDERMANN, GERBAULET & HOFMANN, 20354 HA

8364 No opposition during term of opposition