DE60319939D1 - Verfahren zum Fliess-Glätten leitender Anschlüsse - Google Patents
Verfahren zum Fliess-Glätten leitender AnschlüsseInfo
- Publication number
- DE60319939D1 DE60319939D1 DE60319939T DE60319939T DE60319939D1 DE 60319939 D1 DE60319939 D1 DE 60319939D1 DE 60319939 T DE60319939 T DE 60319939T DE 60319939 T DE60319939 T DE 60319939T DE 60319939 D1 DE60319939 D1 DE 60319939D1
- Authority
- DE
- Germany
- Prior art keywords
- smoothing
- flow
- conductive connections
- connections
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000009499 grossing Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01023—Vanadium [V]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2002361683 | 2002-12-13 | ||
JP2002361683 | 2002-12-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60319939D1 true DE60319939D1 (de) | 2008-05-08 |
DE60319939T2 DE60319939T2 (de) | 2009-04-16 |
Family
ID=32322132
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60319939T Expired - Lifetime DE60319939T2 (de) | 2002-12-13 | 2003-12-15 | Verfahren zum Fliess-Glätten leitender Anschlüsse |
Country Status (5)
Country | Link |
---|---|
US (1) | US7208340B2 (de) |
EP (1) | EP1429377B1 (de) |
CN (1) | CN1287434C (de) |
DE (1) | DE60319939T2 (de) |
TW (1) | TWI239607B (de) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI232560B (en) * | 2002-04-23 | 2005-05-11 | Sanyo Electric Co | Semiconductor device and its manufacture |
TWI229435B (en) * | 2002-06-18 | 2005-03-11 | Sanyo Electric Co | Manufacture of semiconductor device |
TWI227550B (en) * | 2002-10-30 | 2005-02-01 | Sanyo Electric Co | Semiconductor device manufacturing method |
JP4130158B2 (ja) * | 2003-06-09 | 2008-08-06 | 三洋電機株式会社 | 半導体装置の製造方法、半導体装置 |
JP4401181B2 (ja) * | 2003-08-06 | 2010-01-20 | 三洋電機株式会社 | 半導体装置及びその製造方法 |
JP4322181B2 (ja) * | 2004-07-29 | 2009-08-26 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP2006093367A (ja) * | 2004-09-24 | 2006-04-06 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
DE102005010308B4 (de) * | 2005-03-03 | 2017-07-27 | First Sensor Microelectronic Packaging Gmbh | Verfahren zur Herstellung von Chips mit lötfähigen Anschlüssen auf der Rückseite |
DE102005049111A1 (de) * | 2005-10-11 | 2007-04-19 | Infineon Technologies Ag | Verfahren zur Herstellung von mikromechanischen Bauteilen in integrierten Schaltungen und Anordnung eines Halbleiters auf einem Substrat |
JP5010244B2 (ja) * | 2005-12-15 | 2012-08-29 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置 |
TWI324800B (en) * | 2005-12-28 | 2010-05-11 | Sanyo Electric Co | Method for manufacturing semiconductor device |
TWI457193B (zh) * | 2006-03-02 | 2014-10-21 | Sumitomo Heavy Industries | Stage device |
TW200737506A (en) * | 2006-03-07 | 2007-10-01 | Sanyo Electric Co | Semiconductor device and manufacturing method of the same |
WO2008018524A1 (en) * | 2006-08-11 | 2008-02-14 | Sanyo Electric Co., Ltd. | Semiconductor device and its manufacturing method |
JP5010247B2 (ja) * | 2006-11-20 | 2012-08-29 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP5301108B2 (ja) * | 2007-04-20 | 2013-09-25 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
JP2009032929A (ja) * | 2007-07-27 | 2009-02-12 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
JP2010103300A (ja) * | 2008-10-23 | 2010-05-06 | Sanyo Electric Co Ltd | 半導体装置及びその製造方法 |
US8298917B2 (en) * | 2009-04-14 | 2012-10-30 | International Business Machines Corporation | Process for wet singulation using a dicing singulation structure |
JP2012039005A (ja) * | 2010-08-10 | 2012-02-23 | Toshiba Corp | 半導体装置およびその製造方法 |
DE102011112659B4 (de) * | 2011-09-06 | 2022-01-27 | Vishay Semiconductor Gmbh | Oberflächenmontierbares elektronisches Bauelement |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6294925A (ja) | 1985-10-21 | 1987-05-01 | Nec Corp | 熱処理装置 |
JPH0482215A (ja) | 1990-07-25 | 1992-03-16 | Sumitomo Electric Ind Ltd | ランプアニール装置 |
US5910687A (en) | 1997-01-24 | 1999-06-08 | Chipscale, Inc. | Wafer fabrication of die-bottom contacts for electronic devices |
US6432744B1 (en) | 1997-11-20 | 2002-08-13 | Texas Instruments Incorporated | Wafer-scale assembly of chip-size packages |
IL123207A0 (en) | 1998-02-06 | 1998-09-24 | Shellcase Ltd | Integrated circuit device |
US6310328B1 (en) | 1998-12-10 | 2001-10-30 | Mattson Technologies, Inc. | Rapid thermal processing chamber for processing multiple wafers |
US6259039B1 (en) * | 1998-12-29 | 2001-07-10 | Intel Corporation | Surface mount connector with pins in vias |
US6534751B2 (en) | 2000-02-28 | 2003-03-18 | Kyocera Corporation | Wafer heating apparatus and ceramic heater, and method for producing the same |
US6970644B2 (en) | 2000-12-21 | 2005-11-29 | Mattson Technology, Inc. | Heating configuration for use in thermal processing chambers |
JP2004534375A (ja) | 2000-12-21 | 2004-11-11 | シェルケース リミティド | パケージ集積回路およびその製造方法 |
JP2003031647A (ja) * | 2001-07-19 | 2003-01-31 | Hitachi Kokusai Electric Inc | 基板処理装置および半導体装置の製造方法 |
US6805279B2 (en) * | 2002-06-27 | 2004-10-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fluxless bumping process using ions |
-
2003
- 2003-12-03 TW TW092133985A patent/TWI239607B/zh not_active IP Right Cessation
- 2003-12-12 CN CNB2003101202924A patent/CN1287434C/zh not_active Expired - Fee Related
- 2003-12-12 US US10/733,799 patent/US7208340B2/en not_active Expired - Lifetime
- 2003-12-15 DE DE60319939T patent/DE60319939T2/de not_active Expired - Lifetime
- 2003-12-15 EP EP03028639A patent/EP1429377B1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN1287434C (zh) | 2006-11-29 |
DE60319939T2 (de) | 2009-04-16 |
TWI239607B (en) | 2005-09-11 |
US20040161920A1 (en) | 2004-08-19 |
US7208340B2 (en) | 2007-04-24 |
EP1429377B1 (de) | 2008-03-26 |
EP1429377A3 (de) | 2005-03-23 |
CN1507020A (zh) | 2004-06-23 |
EP1429377A2 (de) | 2004-06-16 |
TW200416972A (en) | 2004-09-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |