DE60317771D1 - Externe verbindungseinrichtung, host-einrichtung und datenkommunikationssystem - Google Patents

Externe verbindungseinrichtung, host-einrichtung und datenkommunikationssystem

Info

Publication number
DE60317771D1
DE60317771D1 DE60317771T DE60317771T DE60317771D1 DE 60317771 D1 DE60317771 D1 DE 60317771D1 DE 60317771 T DE60317771 T DE 60317771T DE 60317771 T DE60317771 T DE 60317771T DE 60317771 D1 DE60317771 D1 DE 60317771D1
Authority
DE
Germany
Prior art keywords
communication system
data communication
external connection
connection device
host setup
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60317771T
Other languages
English (en)
Other versions
DE60317771T2 (de
Inventor
Hideaki Bando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of DE60317771D1 publication Critical patent/DE60317771D1/de
Application granted granted Critical
Publication of DE60317771T2 publication Critical patent/DE60317771T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Transfer Systems (AREA)
  • Bus Control (AREA)
  • Table Equipment (AREA)
DE60317771T 2002-02-21 2003-02-19 Externe verbindungseinrichtung, host-einrichtung und datenkommunikationssystem Expired - Lifetime DE60317771T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2002045252A JP4178809B2 (ja) 2002-02-21 2002-02-21 外部接続機器及びホスト機器
JP2002045252 2002-02-21
PCT/JP2003/001800 WO2003071437A1 (fr) 2002-02-21 2003-02-19 Dispositif de connexion externe, dispositif hote et systeme de communication de donnees

Publications (2)

Publication Number Publication Date
DE60317771D1 true DE60317771D1 (de) 2008-01-10
DE60317771T2 DE60317771T2 (de) 2008-12-04

Family

ID=27750574

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60317771T Expired - Lifetime DE60317771T2 (de) 2002-02-21 2003-02-19 Externe verbindungseinrichtung, host-einrichtung und datenkommunikationssystem

Country Status (7)

Country Link
US (2) US7051128B2 (de)
EP (1) EP1477902B1 (de)
JP (1) JP4178809B2 (de)
KR (1) KR100987205B1 (de)
CN (1) CN1297915C (de)
DE (1) DE60317771T2 (de)
WO (1) WO2003071437A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005222201A (ja) * 2004-02-04 2005-08-18 Matsushita Electric Ind Co Ltd メモリアクセス装置、及び半導体メモリカード
EP2506486A1 (de) 2004-02-23 2012-10-03 Lexar Media, Inc. Sicherer kompakter Flash
US7664902B1 (en) * 2004-03-16 2010-02-16 Super Talent Electronics, Inc. Extended SD and microSD hosts and devices with USB-like high performance packetized interface and protocol
KR100909364B1 (ko) 2007-02-06 2009-07-24 삼성전자주식회사 시스템 클록의 노출을 차단하는 메모리 컨트롤러와 그 방법
US7870305B2 (en) * 2007-03-09 2011-01-11 Microsoft Corporation Proxy association for devices
US8064205B2 (en) * 2008-05-19 2011-11-22 Dell Products, Lp Storage devices including different sets of contacts
US20100030962A1 (en) * 2008-08-04 2010-02-04 Sherif Sirageldin Storage facility for data handling devices
TW201145034A (en) * 2010-06-01 2011-12-16 Etron Technology Inc System of realizing multi-port storages based on a UASP protocol of a USB specification version 3.0 and method thereof
JP5673949B2 (ja) * 2011-03-18 2015-02-18 大日本印刷株式会社 内部状態に応じたフォーマット処理を実行できる半導体記憶装置及び半導体記憶装置のフォーマット処理方法
JP5694101B2 (ja) * 2011-09-20 2015-04-01 株式会社東芝 メモリ・デバイス、ホスト・デバイス
USD729808S1 (en) 2013-03-13 2015-05-19 Nagrastar Llc Smart card interface
USD758372S1 (en) 2013-03-13 2016-06-07 Nagrastar Llc Smart card interface
US9647997B2 (en) 2013-03-13 2017-05-09 Nagrastar, Llc USB interface for performing transport I/O
USD759022S1 (en) 2013-03-13 2016-06-14 Nagrastar Llc Smart card interface
US9888283B2 (en) 2013-03-13 2018-02-06 Nagrastar Llc Systems and methods for performing transport I/O
USD780763S1 (en) 2015-03-20 2017-03-07 Nagrastar Llc Smart card interface
USD864968S1 (en) 2015-04-30 2019-10-29 Echostar Technologies L.L.C. Smart card interface

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5416945A (en) * 1977-07-08 1979-02-07 Nippon Telegr & Teleph Corp <Ntt> Signal transmission system
JPS5614329A (en) * 1979-07-16 1981-02-12 Nec Corp Data processing system
US5805844A (en) * 1996-10-07 1998-09-08 Gustin; Jay W. Control circuit for an interface between a PCI bus and a module bus
JPH117505A (ja) * 1997-06-17 1999-01-12 Fujitsu Ltd カード型記憶媒体
IT1308343B1 (it) * 1999-02-03 2001-12-11 St Microelectronics Srl Procedimento per arbitrare priorita' di interruzione tra periferichein un sistema basato su microprocessore
US6618789B1 (en) * 1999-04-07 2003-09-09 Sony Corporation Security memory card compatible with secure and non-secure data processing systems
US6839857B2 (en) * 2000-01-13 2005-01-04 Sony Computer Entertainment Inc. Interrupt controller in an interface device or information processing system
JP2001202254A (ja) * 2000-01-21 2001-07-27 Yaskawa Electric Corp マイクロプロセッサシステム

Also Published As

Publication number Publication date
US20040172488A1 (en) 2004-09-02
US7051128B2 (en) 2006-05-23
CN1507590A (zh) 2004-06-23
US20060143312A1 (en) 2006-06-29
CN1297915C (zh) 2007-01-31
EP1477902A1 (de) 2004-11-17
KR20040086502A (ko) 2004-10-11
JP2003241908A (ja) 2003-08-29
DE60317771T2 (de) 2008-12-04
EP1477902A4 (de) 2006-09-06
US7318113B2 (en) 2008-01-08
KR100987205B1 (ko) 2010-10-12
EP1477902B1 (de) 2007-11-28
WO2003071437A1 (fr) 2003-08-28
JP4178809B2 (ja) 2008-11-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition