DE60314525D1 - Reset-Modus für Scan-Test-Modi - Google Patents

Reset-Modus für Scan-Test-Modi

Info

Publication number
DE60314525D1
DE60314525D1 DE60314525T DE60314525T DE60314525D1 DE 60314525 D1 DE60314525 D1 DE 60314525D1 DE 60314525 T DE60314525 T DE 60314525T DE 60314525 T DE60314525 T DE 60314525T DE 60314525 D1 DE60314525 D1 DE 60314525D1
Authority
DE
Germany
Prior art keywords
scan test
reset mode
test modes
modes
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60314525T
Other languages
English (en)
Other versions
DE60314525T2 (de
Inventor
Bob Warren
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Application granted granted Critical
Publication of DE60314525D1 publication Critical patent/DE60314525D1/de
Publication of DE60314525T2 publication Critical patent/DE60314525T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G01R31/318563—Multiple simultaneous testing of subparts
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60314525T 2003-12-17 2003-12-17 TAP Zeitmultiplexen mit Abtasttest Expired - Lifetime DE60314525T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03257952A EP1544631B1 (de) 2003-12-17 2003-12-17 Reset-Modus für Scan-Test-Modi

Publications (2)

Publication Number Publication Date
DE60314525D1 true DE60314525D1 (de) 2007-08-02
DE60314525T2 DE60314525T2 (de) 2008-02-28

Family

ID=34486432

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60314525T Expired - Lifetime DE60314525T2 (de) 2003-12-17 2003-12-17 TAP Zeitmultiplexen mit Abtasttest

Country Status (3)

Country Link
US (3) US7702974B2 (de)
EP (1) EP1544631B1 (de)
DE (1) DE60314525T2 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7725791B2 (en) * 2006-10-20 2010-05-25 Texas Instruments Incorporated Single lead alternating TDI/TMS DDR JTAG input
US8112683B1 (en) * 2007-02-06 2012-02-07 Marvell International Ltd. System and application debugging
US8589714B2 (en) 2009-12-18 2013-11-19 Texas Instruments Incorporated Falling clock edge JTAG bus routers
KR101910933B1 (ko) * 2011-12-21 2018-10-24 에스케이하이닉스 주식회사 반도체 집적회로 및 그의 테스트 제어방법
US8914693B2 (en) 2012-02-15 2014-12-16 International Business Machines Corporation Apparatus for JTAG-driven remote scanning
US9026872B2 (en) * 2012-08-16 2015-05-05 Xilinx, Inc. Flexible sized die for use in multi-die integrated circuit
US9547034B2 (en) 2013-07-03 2017-01-17 Xilinx, Inc. Monolithic integrated circuit die having modular die regions stitched together
US9915869B1 (en) 2014-07-01 2018-03-13 Xilinx, Inc. Single mask set used for interposer fabrication of multiple products
KR101787889B1 (ko) 2016-04-26 2017-10-19 한양대학교 에리카산학협력단 반도체 회로의 시분할 테스트 방법 및 시스템
KR101856847B1 (ko) 2016-06-14 2018-05-10 한양대학교 에리카산학협력단 적층 반도체 회로의 시분할 테스트 방법 및 장치
US11436181B2 (en) 2016-06-30 2022-09-06 Copper Inc. Data processing systems and methods for transmitting and modifying data via a smart data cable
US20180005218A1 (en) 2016-06-30 2018-01-04 Copper LLC Smart data cable for point of sale systems
US10386411B2 (en) * 2017-08-23 2019-08-20 Stmicroelectronics International N.V. Sequential test access port selection in a JTAG interface
US20220023093A1 (en) * 2020-07-27 2022-01-27 Toshio Hosogai Dual use interoral protection mask
US11132667B1 (en) 2020-12-10 2021-09-28 Copper Inc. Data processing systems and methods for transmitting and modifying data via a smart data cable
US11321693B1 (en) 2020-12-10 2022-05-03 Copper Inc. Data processing systems and methods for transmitting and modifying data via a smart data cable
US20230204662A1 (en) * 2021-12-28 2023-06-29 Advanced Micro Devices Products (China) Co. Ltd., On-chip distribution of test data for multiple dies

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5130988A (en) * 1990-09-17 1992-07-14 Northern Telecom Limited Software verification by fault insertion
US5640521A (en) * 1992-06-17 1997-06-17 Texas Instruments Incorporated Addressable shadow port and protocol with remote I/O, contol and interrupt ports
US5627842A (en) * 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5717947A (en) * 1993-03-31 1998-02-10 Motorola, Inc. Data processing system and method thereof
US5828825A (en) * 1993-12-22 1998-10-27 Intel Corporation Method and apparatus for pseudo-direct access to embedded memories of a micro-controller integrated circuit via the IEEE test access port
GB9417591D0 (en) 1994-09-01 1994-10-19 Inmos Ltd Scan testable double edge triggered scan cell
US5742695A (en) * 1994-11-02 1998-04-21 Advanced Micro Devices, Inc. Wavetable audio synthesizer with waveform volume control for eliminating zipper noise
US6324614B1 (en) * 1997-08-26 2001-11-27 Lee D. Whetsel Tap with scannable control circuit for selecting first test data register in tap or second test data register in tap linking module for scanning data
US6408413B1 (en) * 1998-02-18 2002-06-18 Texas Instruments Incorporated Hierarchical access of test access ports in embedded core integrated circuits
US6425100B1 (en) * 1998-04-24 2002-07-23 Texas Instruments Incorporated Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port
JP3763385B2 (ja) * 1999-11-09 2006-04-05 シャープ株式会社 半導体装置
US7181705B2 (en) * 2000-01-18 2007-02-20 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
US6715105B1 (en) * 2000-11-14 2004-03-30 Agilent Technologies, Inc. Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
US6691270B2 (en) * 2000-12-22 2004-02-10 Arm Limited Integrated circuit and method of operation of such a circuit employing serial test scan chains
US6829730B2 (en) * 2001-04-27 2004-12-07 Logicvision, Inc. Method of designing circuit having multiple test access ports, circuit produced thereby and method of using same
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits
US6816991B2 (en) 2001-11-27 2004-11-09 Sun Microsystems, Inc. Built-in self-testing for double data rate input/output
KR100430074B1 (ko) * 2002-01-08 2004-05-03 학교법인 한양학원 시스템칩 테스트 접근을 위한 랩드 코아 연결 모듈

Also Published As

Publication number Publication date
US20050216802A1 (en) 2005-09-29
US20100192031A1 (en) 2010-07-29
EP1544631B1 (de) 2007-06-20
DE60314525T2 (de) 2008-02-28
US20120266037A1 (en) 2012-10-18
US8412989B2 (en) 2013-04-02
US8151151B2 (en) 2012-04-03
EP1544631A1 (de) 2005-06-22
US7702974B2 (en) 2010-04-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition