DE60314020D1 - Sd-modulator einer pll-schaltung - Google Patents
Sd-modulator einer pll-schaltungInfo
- Publication number
- DE60314020D1 DE60314020D1 DE60314020T DE60314020T DE60314020D1 DE 60314020 D1 DE60314020 D1 DE 60314020D1 DE 60314020 T DE60314020 T DE 60314020T DE 60314020 T DE60314020 T DE 60314020T DE 60314020 D1 DE60314020 D1 DE 60314020D1
- Authority
- DE
- Germany
- Prior art keywords
- modulator
- pll switching
- pll
- switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3006—Compensating for, or preventing of, undesired influence of physical parameters
- H03M7/3011—Compensating for, or preventing of, undesired influence of physical parameters of non-linear distortion, e.g. by temporarily adapting the operation upon detection of instability conditions
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
- H03M7/3002—Conversion to or from differential modulation
- H03M7/3004—Digital delta-sigma modulation
- H03M7/3015—Structural details of digital delta-sigma modulators
- H03M7/302—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M7/3022—Structural details of digital delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2003/015215 WO2005053162A1 (ja) | 2003-11-28 | 2003-11-28 | Pll回路のσδ変調器 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60314020D1 true DE60314020D1 (de) | 2007-07-05 |
DE60314020T2 DE60314020T2 (de) | 2007-09-13 |
Family
ID=34631278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60314020T Expired - Lifetime DE60314020T2 (de) | 2003-11-28 | 2003-11-28 | Sd-modulator einer pll-schaltung |
Country Status (6)
Country | Link |
---|---|
US (1) | US7279990B2 (de) |
EP (1) | EP1657821B1 (de) |
JP (1) | JP4050298B2 (de) |
CN (1) | CN100571040C (de) |
DE (1) | DE60314020T2 (de) |
WO (1) | WO2005053162A1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7916824B2 (en) * | 2006-08-18 | 2011-03-29 | Texas Instruments Incorporated | Loop bandwidth enhancement technique for a digital PLL and a HF divider that enables this technique |
JP4827764B2 (ja) * | 2007-02-20 | 2011-11-30 | 富士通セミコンダクター株式会社 | 分数分周pll装置、およびその制御方法 |
DE102007031127A1 (de) * | 2007-06-29 | 2009-01-02 | IHP GmbH - Innovations for High Performance Microelectronics/Institut für innovative Mikroelektronik | PLL-Schaltung für Frequenzverhältnisse mit nichtganzzahligen Werten |
KR101419892B1 (ko) * | 2007-12-07 | 2014-07-16 | 삼성전자주식회사 | 수신기 및 이를 포함하는 통신 시스템 |
US8169351B2 (en) * | 2009-10-23 | 2012-05-01 | Qualcomm Incorporated | Feedback circuits with DC offset cancellation |
US8193963B2 (en) | 2010-09-02 | 2012-06-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and system for time to digital conversion with calibration and correction loops |
US8228221B2 (en) | 2010-09-28 | 2012-07-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method and apparatus for calibrating sigma-delta modulator |
WO2012127579A1 (ja) * | 2011-03-18 | 2012-09-27 | 富士通株式会社 | Mash方式シグマデルタ・モジュレータおよびda変換回路 |
CN103493377B (zh) * | 2011-06-01 | 2017-04-26 | 华为技术有限公司 | 锁相环中的杂散抑制 |
JP6615418B2 (ja) * | 2017-07-04 | 2019-12-04 | 三菱電機株式会社 | Pll回路 |
JP2020088706A (ja) * | 2018-11-29 | 2020-06-04 | セイコーエプソン株式会社 | 発振器、電子機器及び移動体 |
US11356112B1 (en) * | 2021-01-27 | 2022-06-07 | Infineon Technologies Ag | Coarse-fine counting architecture for a VCO-ADC based on interlocked binary asynchronous counters |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5093632A (en) * | 1990-08-31 | 1992-03-03 | Motorola, Inc. | Latched accumulator fractional n synthesis with residual error reduction |
JP2003023351A (ja) * | 2001-07-09 | 2003-01-24 | Nec Corp | 非整数分周器、およびフラクショナルn周波数シンセサイザ |
US6570452B2 (en) * | 2001-09-26 | 2003-05-27 | Ashvattha Semiconductor, Inc. | Fractional-N type frequency synthesizer |
WO2004062107A1 (ja) * | 2002-12-26 | 2004-07-22 | Fujitsu Limited | Pll回路のσδ変調器 |
-
2003
- 2003-11-28 WO PCT/JP2003/015215 patent/WO2005053162A1/ja active IP Right Grant
- 2003-11-28 CN CNB2003801104756A patent/CN100571040C/zh not_active Expired - Fee Related
- 2003-11-28 DE DE60314020T patent/DE60314020T2/de not_active Expired - Lifetime
- 2003-11-28 JP JP2005510914A patent/JP4050298B2/ja not_active Expired - Fee Related
- 2003-11-28 EP EP03819067A patent/EP1657821B1/de not_active Expired - Fee Related
-
2006
- 2006-02-28 US US11/363,049 patent/US7279990B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPWO2005053162A1 (ja) | 2007-06-21 |
JP4050298B2 (ja) | 2008-02-20 |
EP1657821A4 (de) | 2006-08-23 |
CN100571040C (zh) | 2009-12-16 |
CN1839549A (zh) | 2006-09-27 |
EP1657821B1 (de) | 2007-05-23 |
WO2005053162A1 (ja) | 2005-06-09 |
EP1657821A1 (de) | 2006-05-17 |
US7279990B2 (en) | 2007-10-09 |
US20060139194A1 (en) | 2006-06-29 |
DE60314020T2 (de) | 2007-09-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602004026540D1 (de) | Kurbelwellenmomentmodulator | |
NO20040686L (no) | Forbindelser som pavirker glukokinase | |
DE602004031875D1 (de) | Cb1-modulatorverbindungen | |
DE60328925D1 (de) | Jittergenerator | |
DE60209565D1 (de) | Verstärkermodulation | |
IS6971A (is) | Ný efnasambönd | |
NO20033733L (no) | Festeinnretning for sternum | |
ATE456558T1 (de) | Gabanerge modulatoren | |
DE502004011058D1 (de) | Fallhäufigkeit | |
DE602004030078D1 (de) | Frequenzumrichter | |
DE60314020D1 (de) | Sd-modulator einer pll-schaltung | |
NO20035183D0 (no) | 5-substituerte-2-arylpyridiner som CRF1 modulatorer | |
DE602004027214D1 (de) | Schaltelement | |
DE50302584D1 (de) | Stereomikroskop | |
DE602004012925D1 (de) | Protokoll zur Erbringung von Diensten | |
DE50302514D1 (de) | Stereomikroskop | |
DE60201256D1 (de) | Elektrooptischer wanderwellenmodulator | |
DE60231286D1 (de) | Optischer Modulator | |
DK1597366T3 (da) | Modulering af ekspression af insulin-lignende vækstfaktor receptor I | |
DE602004018247D1 (de) | Modulator | |
SE0500656L (sv) | Spridare | |
ITMC20010025U1 (it) | Doccia multifunzionale | |
NO20033191D0 (no) | Fargemodulator | |
DE602004007010D1 (de) | Bereitstellung von lokalen oszillatorsignalen | |
DE60322635D1 (de) | Geschalteter Modulator |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |