DE60311199D1 - Vorrichtung und Verfahren, um einen Speicher in Selbstauffrischungsbetrieb zu schalten - Google Patents
Vorrichtung und Verfahren, um einen Speicher in Selbstauffrischungsbetrieb zu schaltenInfo
- Publication number
- DE60311199D1 DE60311199D1 DE60311199T DE60311199T DE60311199D1 DE 60311199 D1 DE60311199 D1 DE 60311199D1 DE 60311199 T DE60311199 T DE 60311199T DE 60311199 T DE60311199 T DE 60311199T DE 60311199 D1 DE60311199 D1 DE 60311199D1
- Authority
- DE
- Germany
- Prior art keywords
- switching
- self
- memory
- refresh mode
- refresh
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/219,376 US7139937B1 (en) | 2002-08-15 | 2002-08-15 | Method and apparatus to establish safe state in a volatile computer memory under multiple hardware and software malfunction conditions |
US219376 | 2002-08-15 | ||
US10/407,533 US7200711B2 (en) | 2002-08-15 | 2003-04-04 | Apparatus and method for placing memory into self-refresh state |
US407533 | 2003-04-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60311199D1 true DE60311199D1 (de) | 2007-03-08 |
DE60311199T2 DE60311199T2 (de) | 2007-11-08 |
Family
ID=31498057
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60311199T Expired - Fee Related DE60311199T2 (de) | 2002-08-15 | 2003-08-15 | Vorrichtung und Verfahren, um einen Speicher in Selbstauffrischungsbetrieb zu schalten |
Country Status (4)
Country | Link |
---|---|
US (1) | US7200711B2 (de) |
EP (1) | EP1394807B1 (de) |
JP (1) | JP4511140B2 (de) |
DE (1) | DE60311199T2 (de) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4778694B2 (ja) * | 2004-09-14 | 2011-09-21 | パナソニック株式会社 | 半導体集積回路 |
JP4200969B2 (ja) * | 2004-12-03 | 2008-12-24 | セイコーエプソン株式会社 | 半導体装置及び電子機器 |
US20080028136A1 (en) * | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8077535B2 (en) * | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US7472220B2 (en) * | 2006-07-31 | 2008-12-30 | Metaram, Inc. | Interface circuit system and method for performing power management operations utilizing power management signals |
US7609567B2 (en) * | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US9542352B2 (en) * | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8090897B2 (en) * | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US7386656B2 (en) * | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US20080126690A1 (en) * | 2006-02-09 | 2008-05-29 | Rajan Suresh N | Memory module with memory stack |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8359187B2 (en) * | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US20070014168A1 (en) * | 2005-06-24 | 2007-01-18 | Rajan Suresh N | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies |
US7580312B2 (en) * | 2006-07-31 | 2009-08-25 | Metaram, Inc. | Power saving system and method for use with a plurality of memory circuits |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8041881B2 (en) * | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
KR101303518B1 (ko) * | 2005-09-02 | 2013-09-03 | 구글 인코포레이티드 | Dram 적층 방법 및 장치 |
TWI308694B (en) * | 2005-12-13 | 2009-04-11 | Wistron Corp | Method of data protection for computers |
US20070168740A1 (en) * | 2006-01-10 | 2007-07-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and apparatus for dumping a process memory space |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
US7447096B2 (en) * | 2006-05-05 | 2008-11-04 | Honeywell International Inc. | Method for refreshing a non-volatile memory |
US20080028135A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | Multiple-component memory interface system and method |
US20080025136A1 (en) * | 2006-07-31 | 2008-01-31 | Metaram, Inc. | System and method for storing at least a portion of information received in association with a first operation for use in performing a second operation |
US7724589B2 (en) * | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
US7616508B1 (en) * | 2006-08-10 | 2009-11-10 | Actel Corporation | Flash-based FPGA with secure reprogramming |
US8209479B2 (en) * | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
US20090089514A1 (en) * | 2007-09-28 | 2009-04-02 | Durgesh Srivastava | Implementing Asynchronous Request for Forcing Dynamic Memory into Self Refresh |
DE202010017690U1 (de) * | 2009-06-09 | 2012-05-29 | Google, Inc. | Programmierung von Dimm-Abschlusswiderstandswerten |
US8694812B2 (en) * | 2010-03-29 | 2014-04-08 | Dot Hill Systems Corporation | Memory calibration method and apparatus for power reduction during flash operation |
US9014749B2 (en) | 2010-08-12 | 2015-04-21 | Qualcomm Incorporated | System and method to initiate a housekeeping operation at a mobile device |
US9530483B2 (en) | 2014-05-27 | 2016-12-27 | Src Labs, Llc | System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem |
US9153311B1 (en) * | 2014-05-27 | 2015-10-06 | SRC Computers, LLC | System and method for retaining DRAM data when reprogramming reconfigurable devices with DRAM memory controllers |
US9537979B2 (en) * | 2014-12-12 | 2017-01-03 | Intel Corporation | Network adapter optical alert system |
US9568971B2 (en) | 2015-02-05 | 2017-02-14 | Apple Inc. | Solid state drive with self-refresh power saving mode |
US10127968B2 (en) | 2015-08-03 | 2018-11-13 | Intel Corporation | Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4710903A (en) * | 1986-03-31 | 1987-12-01 | Wang Laboratories, Inc. | Pseudo-static memory subsystem |
JPS62293593A (ja) * | 1986-06-13 | 1987-12-21 | Fujitsu Ltd | メモリバツクアツプ制御回路 |
US4979171A (en) | 1989-05-03 | 1990-12-18 | Rockwell International Corporation | Announcement and tone code generator for telephonic network and method |
US5175853A (en) | 1990-10-09 | 1992-12-29 | Intel Corporation | Transparent system interrupt |
US5781784A (en) | 1992-07-09 | 1998-07-14 | Zilog, Inc. | Dynamic power management of solid state memories |
JPH07182857A (ja) | 1993-12-24 | 1995-07-21 | Toshiba Corp | マイコンシステム |
JP3524151B2 (ja) * | 1994-04-28 | 2004-05-10 | キヤノン株式会社 | メモリバックアップ制御装置 |
US5692202A (en) | 1995-12-29 | 1997-11-25 | Intel Corporation | System, apparatus, and method for managing power in a computer system |
US5935259A (en) | 1996-09-24 | 1999-08-10 | Apple Computer, Inc. | System and method for preventing damage to media files within a digital camera device |
US6216233B1 (en) * | 1997-02-12 | 2001-04-10 | Intel Corporation | Maintaining a memory while in a power management mode |
JPH10228768A (ja) * | 1997-02-14 | 1998-08-25 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6212599B1 (en) | 1997-11-26 | 2001-04-03 | Intel Corporation | Method and apparatus for a memory control system including a secondary controller for DRAM refresh during sleep mode |
US6088762A (en) * | 1998-06-19 | 2000-07-11 | Intel Corporation | Power failure mode for a memory controller |
US6317657B1 (en) | 1998-08-18 | 2001-11-13 | International Business Machines Corporation | Method to battery back up SDRAM data on power failure |
US6119200A (en) | 1998-08-18 | 2000-09-12 | Mylex Corporation | System and method to protect SDRAM data during warm resets |
KR100381966B1 (ko) | 1998-12-28 | 2004-03-22 | 주식회사 하이닉스반도체 | 반도체메모리장치및그구동방법 |
JP3588267B2 (ja) * | 1999-03-05 | 2004-11-10 | 三洋電機株式会社 | リフレッシュ回路及びそれを用いた光ディスク再生装置の制御回路 |
US6633987B2 (en) * | 2000-03-24 | 2003-10-14 | Intel Corporation | Method and apparatus to implement the ACPI(advanced configuration and power interface) C3 state in a RDRAM based system |
JP2002041445A (ja) | 2000-05-19 | 2002-02-08 | Matsushita Electric Ind Co Ltd | 高性能dmaコントローラ |
-
2003
- 2003-04-04 US US10/407,533 patent/US7200711B2/en not_active Expired - Fee Related
- 2003-08-14 JP JP2003293489A patent/JP4511140B2/ja not_active Expired - Lifetime
- 2003-08-15 EP EP03255094A patent/EP1394807B1/de not_active Expired - Lifetime
- 2003-08-15 DE DE60311199T patent/DE60311199T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7200711B2 (en) | 2007-04-03 |
EP1394807A2 (de) | 2004-03-03 |
JP2005115972A (ja) | 2005-04-28 |
JP4511140B2 (ja) | 2010-07-28 |
EP1394807B1 (de) | 2007-01-17 |
EP1394807A3 (de) | 2004-09-01 |
DE60311199T2 (de) | 2007-11-08 |
US20040034732A1 (en) | 2004-02-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |