DE60306982D1 - Digital-Analog-Wandler, Verzögerungsregelschleife, Speichergerät und Zählverfahren - Google Patents

Digital-Analog-Wandler, Verzögerungsregelschleife, Speichergerät und Zählverfahren

Info

Publication number
DE60306982D1
DE60306982D1 DE60306982T DE60306982T DE60306982D1 DE 60306982 D1 DE60306982 D1 DE 60306982D1 DE 60306982 T DE60306982 T DE 60306982T DE 60306982 T DE60306982 T DE 60306982T DE 60306982 D1 DE60306982 D1 DE 60306982D1
Authority
DE
Germany
Prior art keywords
digital
storage device
analog converter
locked loop
delay locked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60306982T
Other languages
English (en)
Other versions
DE60306982T2 (de
Inventor
In-Young Chung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Application granted granted Critical
Publication of DE60306982D1 publication Critical patent/DE60306982D1/de
Publication of DE60306982T2 publication Critical patent/DE60306982T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0687—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using fault-tolerant coding, e.g. parity check, error correcting codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/16—Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
    • H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/664—Non-linear conversion not otherwise provided for in subgroups of H03M1/66
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/74—Simultaneous conversion
    • H03M1/742—Simultaneous conversion using current sources as quantisation value generators
    • H03M1/745—Simultaneous conversion using current sources as quantisation value generators with weighted currents

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE60306982T 2002-05-06 2003-01-28 Digital-Analog-Wandler, Verzögerungsregelschleife, Speichergerät und Zählverfahren Expired - Lifetime DE60306982T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2002-0024738A KR100454129B1 (ko) 2002-05-06 2002-05-06 코드 변환 장치, 디지털-아날로그 변환 장치, 그리고 지연동기 루프회로
KR2002024738 2002-05-06

Publications (2)

Publication Number Publication Date
DE60306982D1 true DE60306982D1 (de) 2006-09-07
DE60306982T2 DE60306982T2 (de) 2007-03-29

Family

ID=36848401

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60306982T Expired - Lifetime DE60306982T2 (de) 2002-05-06 2003-01-28 Digital-Analog-Wandler, Verzögerungsregelschleife, Speichergerät und Zählverfahren

Country Status (6)

Country Link
US (2) US6778114B2 (de)
EP (1) EP1361661B1 (de)
JP (1) JP3911490B2 (de)
KR (1) KR100454129B1 (de)
CN (1) CN100474779C (de)
DE (1) DE60306982T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7088129B2 (en) * 2004-04-30 2006-08-08 Avago Technologies General Ip (Singapore) Pte. Ltd. Hybrid binary/thermometer code for controlled-voltage integrated circuit output drivers
US7664216B2 (en) * 2004-08-05 2010-02-16 Micron Technology, Inc. Digital frequency locked delay line
US7990047B2 (en) 2005-10-28 2011-08-02 Samsung Electronics Co., Ltd. Organic light emitting diode display and method of manufacturing the same
KR101143006B1 (ko) 2005-10-28 2012-05-08 삼성전자주식회사 유기 발광 표시 장치 및 그 제조 방법
WO2009125580A1 (ja) * 2008-04-11 2009-10-15 株式会社アドバンテスト ループ型クロック調整回路および試験装置
KR101050403B1 (ko) * 2009-07-03 2011-07-19 주식회사 하이닉스반도체 지연라인
US8289062B2 (en) * 2010-09-16 2012-10-16 Micron Technology, Inc. Analog delay lines and adaptive biasing
US8928387B2 (en) * 2013-05-10 2015-01-06 Laurence H. Cooke Tunable clock distribution system
KR20170132392A (ko) * 2016-05-23 2017-12-04 삼성전자주식회사 지연 코드 생성기를 포함하는 지연 고정 회로
WO2018133927A1 (en) * 2017-01-18 2018-07-26 Huawei Technologies Co., Ltd. Digital-to-analog converter circuit with two encoding schemes
US11094354B2 (en) * 2019-10-10 2021-08-17 Stmicroelectronics International N.V. First order memory-less dynamic element matching technique
US10895848B1 (en) * 2020-03-17 2021-01-19 Semiconductor Components Industries, Llc Methods and apparatus for selective histogramming
CN111366358B (zh) * 2020-03-20 2021-11-19 首钢京唐钢铁联合有限责任公司 一种升降丝杠的故障检测装置及方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3573797A (en) * 1968-10-24 1971-04-06 Nasa Rate augmented digital-to-analog converter
US4795314A (en) * 1987-08-24 1989-01-03 Cobe Laboratories, Inc. Condition responsive pump control utilizing integrated, commanded, and sensed flowrate signals
JPH0697832A (ja) * 1992-09-14 1994-04-08 Matsushita Electric Ind Co Ltd 符号変換回路およびそれを備えたａ／ｄ変換器
JPH09116438A (ja) * 1995-10-23 1997-05-02 Yamatake Honeywell Co Ltd ディジタル／アナログ変換器
KR100218329B1 (ko) * 1996-11-08 1999-09-01 구본준 고속 저전력 디지탈 아날로그 컨버터
US6104225A (en) * 1997-04-21 2000-08-15 Fujitsu Limited Semiconductor device using complementary clock and signal input state detection circuit used for the same
CA2204089C (en) * 1997-04-30 2001-08-07 Mosaid Technologies Incorporated Digital delay locked loop
GB2333171A (en) * 1998-01-08 1999-07-14 Fujitsu Microelectronics Ltd Thermometer coding circuitry
US6327318B1 (en) * 1998-06-30 2001-12-04 Mosaid Technologies Incorporated Process, voltage, temperature independent switched delay compensation scheme
KR100304955B1 (ko) * 1998-08-20 2001-09-24 김영환 디지털/아날로그변환기
JP4397076B2 (ja) * 1999-08-20 2010-01-13 株式会社ルネサステクノロジ 半導体装置
US6480439B2 (en) * 2000-10-03 2002-11-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JP2002124873A (ja) * 2000-10-18 2002-04-26 Mitsubishi Electric Corp 半導体装置
US6680634B1 (en) * 2002-12-03 2004-01-20 Nokia Corporation Self calibrating digital delay-locked loop

Also Published As

Publication number Publication date
JP2004007635A (ja) 2004-01-08
US20040196079A1 (en) 2004-10-07
US6847242B2 (en) 2005-01-25
CN1457149A (zh) 2003-11-19
US20030206043A1 (en) 2003-11-06
EP1361661A2 (de) 2003-11-12
DE60306982T2 (de) 2007-03-29
CN100474779C (zh) 2009-04-01
KR100454129B1 (ko) 2004-10-26
US6778114B2 (en) 2004-08-17
JP3911490B2 (ja) 2007-05-09
KR20030086644A (ko) 2003-11-12
EP1361661A3 (de) 2004-08-18
EP1361661B1 (de) 2006-07-26

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Legal Events

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