DE60306029D1 - Speichervorrichtung mit vernetztem Zellenfeld - Google Patents

Speichervorrichtung mit vernetztem Zellenfeld

Info

Publication number
DE60306029D1
DE60306029D1 DE60306029T DE60306029T DE60306029D1 DE 60306029 D1 DE60306029 D1 DE 60306029D1 DE 60306029 T DE60306029 T DE 60306029T DE 60306029 T DE60306029 T DE 60306029T DE 60306029 D1 DE60306029 D1 DE 60306029D1
Authority
DE
Germany
Prior art keywords
storage device
cell array
networked cell
networked
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60306029T
Other languages
English (en)
Other versions
DE60306029T2 (de
Inventor
Andrew Koll
Peter Fricke
Brocklin Andrew L Van
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE60306029D1 publication Critical patent/DE60306029D1/de
Application granted granted Critical
Publication of DE60306029T2 publication Critical patent/DE60306029T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
DE60306029T 2002-05-07 2003-04-29 Speichervorrichtung mit vernetztem Zellenfeld Expired - Lifetime DE60306029T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/141,609 US6842369B2 (en) 2002-05-07 2002-05-07 Intermesh memory device
US141609 2002-05-07

Publications (2)

Publication Number Publication Date
DE60306029D1 true DE60306029D1 (de) 2006-07-27
DE60306029T2 DE60306029T2 (de) 2007-06-14

Family

ID=29249818

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60306029T Expired - Lifetime DE60306029T2 (de) 2002-05-07 2003-04-29 Speichervorrichtung mit vernetztem Zellenfeld

Country Status (7)

Country Link
US (1) US6842369B2 (de)
EP (1) EP1361579B1 (de)
JP (1) JP3871651B2 (de)
KR (1) KR100933400B1 (de)
CA (1) CA2424639A1 (de)
DE (1) DE60306029T2 (de)
TW (1) TWI254317B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7035159B2 (en) 2004-04-01 2006-04-25 Micron Technology, Inc. Techniques for storing accurate operating current values
US7120065B2 (en) * 2004-04-01 2006-10-10 Micron Technology, Inc. Techniques for implementing accurate operating current values stored in a database
DK1792482T3 (da) * 2004-09-16 2012-12-10 Trident Microsystems Far East Lageroptimering til videobehandling
JP4231502B2 (ja) * 2005-11-02 2009-03-04 シャープ株式会社 クロスポイント構造の半導体記憶装置
US20090086521A1 (en) * 2007-09-28 2009-04-02 Herner S Brad Multiple antifuse memory cells and methods to form, program, and sense the same
US8866121B2 (en) 2011-07-29 2014-10-21 Sandisk 3D Llc Current-limiting layer and a current-reducing layer in a memory device
US8659001B2 (en) 2011-09-01 2014-02-25 Sandisk 3D Llc Defect gradient to boost nonvolatile memory performance
US8637413B2 (en) 2011-12-02 2014-01-28 Sandisk 3D Llc Nonvolatile resistive memory element with a passivated switching layer
US8698119B2 (en) 2012-01-19 2014-04-15 Sandisk 3D Llc Nonvolatile memory device using a tunnel oxide as a current limiter element
US8686386B2 (en) 2012-02-17 2014-04-01 Sandisk 3D Llc Nonvolatile memory device using a varistor as a current limiter element
US20140241031A1 (en) 2013-02-28 2014-08-28 Sandisk 3D Llc Dielectric-based memory cells having multi-level one-time programmable and bi-level rewriteable operating modes and methods of forming the same

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4287571A (en) * 1979-09-11 1981-09-01 International Business Machines Corporation High density transistor arrays
US4872140A (en) * 1987-05-19 1989-10-03 Gazelle Microcircuits, Inc. Laser programmable memory array
JPH01308070A (ja) * 1988-06-07 1989-12-12 Matsushita Electric Ind Co Ltd 半導体記憶装置
JPH0817039B2 (ja) * 1988-08-19 1996-02-21 株式会社東芝 半導体メモリセル
WO2004090909A1 (ja) * 1994-12-27 2004-10-21 Nobufumi Inada 情報記憶装置およびその動作方法
JP3560266B2 (ja) 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
US5835396A (en) * 1996-10-17 1998-11-10 Zhang; Guobiao Three-dimensional read-only memory
US6288431B1 (en) 1997-04-04 2001-09-11 Nippon Steel Corporation Semiconductor device and a method of manufacturing the same
US6150687A (en) 1997-07-08 2000-11-21 Micron Technology, Inc. Memory cell having a vertical transistor with buried source/drain and dual gates
DE59814170D1 (de) 1997-12-17 2008-04-03 Qimonda Ag Speicherzellenanordnung und Verfahren zu deren Herstellung
US6124729A (en) 1998-02-27 2000-09-26 Micron Technology, Inc. Field programmable logic arrays with vertical transistors
US6351406B1 (en) * 1998-11-16 2002-02-26 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication
JP3307360B2 (ja) 1999-03-10 2002-07-24 日本電気株式会社 半導体集積回路装置
US6462977B2 (en) * 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
US6525953B1 (en) * 2001-08-13 2003-02-25 Matrix Semiconductor, Inc. Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication

Also Published As

Publication number Publication date
TW200306578A (en) 2003-11-16
US6842369B2 (en) 2005-01-11
TWI254317B (en) 2006-05-01
EP1361579A1 (de) 2003-11-12
KR100933400B1 (ko) 2009-12-22
KR20030087548A (ko) 2003-11-14
JP3871651B2 (ja) 2007-01-24
DE60306029T2 (de) 2007-06-14
JP2003338606A (ja) 2003-11-28
CA2424639A1 (en) 2003-11-07
US20030210567A1 (en) 2003-11-13
EP1361579B1 (de) 2006-06-14

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., HOUSTON

8328 Change in the person/name/address of the agent

Representative=s name: SCHOPPE, ZIMMERMANN, STOECKELER & ZINKLER, 82049 PU

8364 No opposition during term of opposition