DE60222055D1 - Taktverteilung mit niedriger Latenz - Google Patents
Taktverteilung mit niedriger LatenzInfo
- Publication number
- DE60222055D1 DE60222055D1 DE60222055T DE60222055T DE60222055D1 DE 60222055 D1 DE60222055 D1 DE 60222055D1 DE 60222055 T DE60222055 T DE 60222055T DE 60222055 T DE60222055 T DE 60222055T DE 60222055 D1 DE60222055 D1 DE 60222055D1
- Authority
- DE
- Germany
- Prior art keywords
- low latency
- clock distribution
- clock
- distribution
- latency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/15—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors
- H03K5/15013—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs
- H03K5/1506—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with more than two outputs with parallel driven output stages; with synchronously driven series connected output stages
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US40750 | 1993-03-31 | ||
US30188401P | 2001-06-29 | 2001-06-29 | |
US301884P | 2001-06-29 | ||
US10/040,750 US6630851B2 (en) | 2001-06-29 | 2001-12-28 | Low latency clock distribution |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60222055D1 true DE60222055D1 (de) | 2007-10-11 |
DE60222055T2 DE60222055T2 (de) | 2007-12-13 |
Family
ID=26717392
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60222055T Expired - Fee Related DE60222055T2 (de) | 2001-06-29 | 2002-06-27 | Taktverteilung mit niedriger Latenz |
Country Status (4)
Country | Link |
---|---|
US (1) | US6630851B2 (de) |
EP (1) | EP1271285B1 (de) |
JP (1) | JP2003122446A (de) |
DE (1) | DE60222055T2 (de) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6668357B2 (en) | 2001-06-29 | 2003-12-23 | Fujitsu Limited | Cold clock power reduction |
WO2003023962A1 (en) * | 2001-09-07 | 2003-03-20 | Xtremespectrum, Inc. | Narrow-pulse-width bipolar monocycle generator |
US7053680B2 (en) * | 2002-06-12 | 2006-05-30 | Fujitsu Limited | Complement reset buffer |
US6577176B1 (en) * | 2002-06-12 | 2003-06-10 | Fujitsu Limited | Complement reset latch |
ITMI20031217A1 (it) * | 2003-06-17 | 2004-12-18 | Atmel Corp | Ripetitore rigenerativo di temporizzazione |
KR100608355B1 (ko) * | 2004-03-25 | 2006-08-08 | 주식회사 하이닉스반도체 | 메모리 장치의 동작 주파수 변동에 따른 내부 제어 신호의인에이블 구간을 제어하는 장치와 그 방법 |
US7405597B1 (en) * | 2005-06-30 | 2008-07-29 | Transmeta Corporation | Advanced repeater with duty cycle adjustment |
US7142018B2 (en) * | 2004-06-08 | 2006-11-28 | Transmeta Corporation | Circuits and methods for detecting and assisting wire transitions |
US7498846B1 (en) | 2004-06-08 | 2009-03-03 | Transmeta Corporation | Power efficient multiplexer |
US7304503B2 (en) * | 2004-06-08 | 2007-12-04 | Transmeta Corporation | Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability |
US7336103B1 (en) * | 2004-06-08 | 2008-02-26 | Transmeta Corporation | Stacked inverter delay chain |
US7071747B1 (en) | 2004-06-15 | 2006-07-04 | Transmeta Corporation | Inverting zipper repeater circuit |
DE102004054546B4 (de) * | 2004-11-11 | 2011-06-22 | Qimonda AG, 81739 | Treiberschaltung |
US7724027B2 (en) * | 2005-03-31 | 2010-05-25 | Rozas Guillermo J | Method and system for elastic signal pipelining |
US7663408B2 (en) * | 2005-06-30 | 2010-02-16 | Robert Paul Masleid | Scannable dynamic circuit latch |
US7256634B2 (en) * | 2005-07-06 | 2007-08-14 | Transmeta Corporation | Elastic pipeline latch with a safe mode |
US7710153B1 (en) | 2006-06-30 | 2010-05-04 | Masleid Robert P | Cross point switch |
US7890684B2 (en) * | 2006-08-31 | 2011-02-15 | Standard Microsystems Corporation | Two-cycle return path clocking |
JP4862680B2 (ja) * | 2007-02-15 | 2012-01-25 | 富士通株式会社 | クロック信号分配回路、情報処理装置及びクロック信号分配方法 |
JP5032637B2 (ja) * | 2010-07-30 | 2012-09-26 | 株式会社東芝 | 増幅器及びそれを用いた無線送信機 |
CN102361453B (zh) * | 2011-08-15 | 2013-01-23 | 中国电子科技集团公司第二十四研究所 | 用于锁相环的高速占空比调节和双端转单端电路 |
WO2013049333A1 (en) * | 2011-09-28 | 2013-04-04 | Panavision Imaging | System and method for delayed clock distribution in column-parallel a/d architectures used in cmos image sensors |
US9459651B2 (en) | 2011-11-04 | 2016-10-04 | Freescale Semiconductor, Inc. | Multi-level clock signal distribution network and integrated circuit |
US9190991B2 (en) | 2011-12-15 | 2015-11-17 | Intel Corporation | Apparatus, system, and method for re-synthesizing a clock signal |
US9876491B2 (en) | 2011-12-15 | 2018-01-23 | Intel Corporation | Apparatus, system, and method for re-synthesizing a clock signal |
US20140266376A1 (en) * | 2013-03-15 | 2014-09-18 | Analog Devices, Inc. | Active clock tree for data converters |
US20180006653A1 (en) * | 2016-06-29 | 2018-01-04 | Altera Corporation | Integrated circuits with hybrid fixed/configurable clock networks |
US10666415B2 (en) | 2017-01-06 | 2020-05-26 | International Business Machines Corporation | Determining clock signal quality using a plurality of sensors |
US10809757B2 (en) * | 2018-10-04 | 2020-10-20 | Mediatek Inc. | Clock buffer having low power, low noise and low spur |
EP3696570B1 (de) * | 2019-02-15 | 2023-07-26 | Stichting IMEC Nederland | Radar-sende-empfänger |
CN113705964B (zh) * | 2021-07-16 | 2024-01-02 | 国网上海市电力公司 | 一种配电网韧性恢复灾前预案制定方法及装置 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4638311A (en) * | 1984-11-13 | 1987-01-20 | Itt Corporation | Apparatus for providing masterless collision detection |
JPH05159080A (ja) * | 1991-12-05 | 1993-06-25 | Hitachi Ltd | 論理集積回路 |
JPH0795022A (ja) * | 1993-09-22 | 1995-04-07 | Toshiba Corp | 遅延回路 |
US5546023A (en) * | 1995-06-26 | 1996-08-13 | Intel Corporation | Daisy chained clock distribution scheme |
US5614845A (en) | 1995-09-08 | 1997-03-25 | International Business Machines Corporation | Independent clock edge regulation |
US5610548A (en) | 1995-09-08 | 1997-03-11 | International Business Machines Corporation | Split drive clock buffer |
US5656963A (en) | 1995-09-08 | 1997-08-12 | International Business Machines Corporation | Clock distribution network for reducing clock skew |
US5926050A (en) * | 1996-07-29 | 1999-07-20 | Townsend And Townsend And Crew Llp | Separate set/reset paths for time critical signals |
US5894419A (en) | 1997-04-21 | 1999-04-13 | International Business Machines Corporation | System and method for robust clocking schemes for logic circuits |
JP3039466B2 (ja) * | 1997-08-12 | 2000-05-08 | 日本電気株式会社 | クロックリカバリ回路 |
US6025738A (en) | 1997-08-22 | 2000-02-15 | International Business Machines Corporation | Gain enhanced split drive buffer |
US6323706B1 (en) * | 2000-02-24 | 2001-11-27 | Rambus Inc. | Apparatus and method for edge based duty cycle conversion |
JP3663486B2 (ja) * | 2000-09-04 | 2005-06-22 | 株式会社日立製作所 | 半導体集積回路 |
US6366115B1 (en) * | 2001-02-21 | 2002-04-02 | Analog Devices, Inc. | Buffer circuit with rising and falling edge propagation delay correction and method |
US6466063B2 (en) * | 2001-03-20 | 2002-10-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Push-pull output buffer with gate voltage feedback loop |
US6426652B1 (en) | 2001-05-14 | 2002-07-30 | Sun Microsystems, Inc. | Dual-edge triggered dynamic logic |
-
2001
- 2001-12-28 US US10/040,750 patent/US6630851B2/en not_active Expired - Fee Related
-
2002
- 2002-06-27 EP EP02014023A patent/EP1271285B1/de not_active Expired - Fee Related
- 2002-06-27 DE DE60222055T patent/DE60222055T2/de not_active Expired - Fee Related
- 2002-07-01 JP JP2002192080A patent/JP2003122446A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE60222055T2 (de) | 2007-12-13 |
EP1271285A3 (de) | 2006-01-04 |
EP1271285B1 (de) | 2007-08-29 |
US20030011413A1 (en) | 2003-01-16 |
EP1271285A2 (de) | 2003-01-02 |
US6630851B2 (en) | 2003-10-07 |
JP2003122446A (ja) | 2003-04-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |