DE60234291D1 - Kalte Taktgeberleistungsverminderung - Google Patents

Kalte Taktgeberleistungsverminderung

Info

Publication number
DE60234291D1
DE60234291D1 DE60234291T DE60234291T DE60234291D1 DE 60234291 D1 DE60234291 D1 DE 60234291D1 DE 60234291 T DE60234291 T DE 60234291T DE 60234291 T DE60234291 T DE 60234291T DE 60234291 D1 DE60234291 D1 DE 60234291D1
Authority
DE
Germany
Prior art keywords
performance degradation
clock performance
cold clock
cold
degradation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60234291T
Other languages
English (en)
Inventor
Robert P Masleid
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE60234291D1 publication Critical patent/DE60234291D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3237—Power saving characterised by the action undertaken by disabling clock generation or distribution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
DE60234291T 2001-06-29 2002-06-27 Kalte Taktgeberleistungsverminderung Expired - Lifetime DE60234291D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US30189001P 2001-06-29 2001-06-29
US10/040,577 US6668357B2 (en) 2001-06-29 2001-12-28 Cold clock power reduction

Publications (1)

Publication Number Publication Date
DE60234291D1 true DE60234291D1 (de) 2009-12-24

Family

ID=26717192

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60234291T Expired - Lifetime DE60234291D1 (de) 2001-06-29 2002-06-27 Kalte Taktgeberleistungsverminderung

Country Status (4)

Country Link
US (2) US6668357B2 (de)
EP (1) EP1271290B1 (de)
JP (1) JP3908618B2 (de)
DE (1) DE60234291D1 (de)

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US6408393B1 (en) * 1998-01-09 2002-06-18 Hitachi, Ltd. CPU power adjustment method
CN1288845C (zh) * 2002-02-21 2006-12-06 皇家飞利浦电子股份有限公司 降低了衬底反弹的集成电路
US7146517B2 (en) * 2002-05-02 2006-12-05 Cray, Inc. Clock pulse shaver with selective enable pulse width
US6738963B2 (en) * 2002-06-28 2004-05-18 Intel Corporation Dynamically reconfiguring clock domains on a chip
DE10355187B4 (de) * 2003-11-26 2006-05-24 Infineon Technologies Ag Verfahren und Vorrichtung zur Timinganalyse einer Schaltung
US7620920B2 (en) * 2004-07-02 2009-11-17 Hewlett-Packard Development Company, L.P. Time separated signals
US20070033427A1 (en) * 2005-07-19 2007-02-08 International Business Machines Corporation Power efficient cycle stealing
US7679401B1 (en) 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US7849349B2 (en) * 2007-03-28 2010-12-07 Qimonda Ag Reduced-delay clocked logic
US7913103B2 (en) * 2007-08-31 2011-03-22 Globalfoundries Inc. Method and apparatus for clock cycle stealing
US8291201B2 (en) * 2008-05-22 2012-10-16 International Business Machines Corporation Dynamic merging of pipeline stages in an execution pipeline to reduce power consumption
US8166435B2 (en) * 2008-06-26 2012-04-24 Tabula, Inc. Timing operations in an IC with configurable circuits
WO2010033263A1 (en) 2008-09-17 2010-03-25 Tabula, Inc. Controllable storage elements for an ic
US8589670B2 (en) * 2009-03-27 2013-11-19 Advanced Micro Devices, Inc. Adjusting system configuration for increased reliability based on margin
US8176354B2 (en) * 2010-03-25 2012-05-08 International Business Machines Corporation Wave pipeline with selectively opaque register stages
US8912820B2 (en) 2010-04-02 2014-12-16 Tabula, Inc. System and method for reducing reconfiguration power
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US8954017B2 (en) * 2011-08-17 2015-02-10 Broadcom Corporation Clock signal multiplication to reduce noise coupled onto a transmission communication signal of a communications device
US10140413B2 (en) * 2015-04-21 2018-11-27 Synopsys, Inc. Efficient resolution of latch race conditions in emulation
US10313108B2 (en) 2016-06-29 2019-06-04 Intel Corporation Energy-efficient bitcoin mining hardware accelerators
US10216875B2 (en) * 2017-02-23 2019-02-26 International Business Machines Corporation Leverage cycle stealing within optimization flows
US11048292B2 (en) 2018-12-13 2021-06-29 Nxp Usa, Inc. Duty cycle control for reduced dynamic power consumption

Family Cites Families (28)

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US11413A (en) * 1854-08-01 Jeremiah carhart
NL8303536A (nl) * 1983-10-14 1985-05-01 Philips Nv Geintegreerde schakeling op grote schaal welke verdeeld is in isochrone gebieden, werkwijze voor het machinaal ontwerpen van zo een geintegreerde schakeling, en werkwijze voor het machinaal testen van zo een geintegreerde schakeling.
US5124572A (en) 1990-11-27 1992-06-23 Hewlett-Packard Co. VLSI clocking system using both overlapping and non-overlapping clocks
US5615126A (en) * 1994-08-24 1997-03-25 Lsi Logic Corporation High-speed internal interconnection technique for integrated circuits that reduces the number of signal lines through multiplexing
EP0724209A1 (de) 1995-01-25 1996-07-31 International Business Machines Corporation Leistungssteuerungssystem für integrierte Schaltungen
US5614845A (en) 1995-09-08 1997-03-25 International Business Machines Corporation Independent clock edge regulation
US5610548A (en) 1995-09-08 1997-03-11 International Business Machines Corporation Split drive clock buffer
US5656963A (en) 1995-09-08 1997-08-12 International Business Machines Corporation Clock distribution network for reducing clock skew
US5675273A (en) 1995-09-08 1997-10-07 International Business Machines Corporation Clock regulator with precision midcycle edge timing
US5742190A (en) 1996-06-27 1998-04-21 Intel Corporation Method and apparatus for clocking latches in a system having both pulse latches and two-phase latches
US5831451A (en) * 1996-07-19 1998-11-03 Texas Instruments Incorporated Dynamic logic circuits using transistors having differing threshold voltages
US5926050A (en) 1996-07-29 1999-07-20 Townsend And Townsend And Crew Llp Separate set/reset paths for time critical signals
US5864487A (en) * 1996-11-19 1999-01-26 Unisys Corporation Method and apparatus for identifying gated clocks within a circuit design using a standard optimization tool
US5956256A (en) * 1996-11-19 1999-09-21 Unisys Corporation Method and apparatus for optimizing a circuit design having multi-paths therein
US5894419A (en) 1997-04-21 1999-04-13 International Business Machines Corporation System and method for robust clocking schemes for logic circuits
US6173432B1 (en) * 1997-06-20 2001-01-09 Micron Technology, Inc. Method and apparatus for generating a sequence of clock signals
US6025738A (en) 1997-08-22 2000-02-15 International Business Machines Corporation Gain enhanced split drive buffer
JP3111936B2 (ja) 1997-09-10 2000-11-27 日本電気株式会社 同期回路
US6118304A (en) * 1997-11-20 2000-09-12 Intrinsity, Inc. Method and apparatus for logic synchronization
US6288589B1 (en) * 1997-11-20 2001-09-11 Intrinsity, Inc. Method and apparatus for generating clock signals
US6188262B1 (en) * 1998-09-04 2001-02-13 Sun Microsystems, Inc. Synchronous polyphase clock distribution system
US6304125B1 (en) * 1998-09-04 2001-10-16 Sun Microsystems, Inc. Method for generating and distribution of polyphase clock signals
US6323706B1 (en) 2000-02-24 2001-11-27 Rambus Inc. Apparatus and method for edge based duty cycle conversion
US6594806B1 (en) * 2000-03-03 2003-07-15 Nec Corporation System and method for performing timing analysis, including error diagnosis, signal tracking and clock skew
US6366115B1 (en) 2001-02-21 2002-04-02 Analog Devices, Inc. Buffer circuit with rising and falling edge propagation delay correction and method
US6466063B2 (en) 2001-03-20 2002-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Push-pull output buffer with gate voltage feedback loop
US6426652B1 (en) 2001-05-14 2002-07-30 Sun Microsystems, Inc. Dual-edge triggered dynamic logic
US6630851B2 (en) 2001-06-29 2003-10-07 Fujitsu Limited Low latency clock distribution

Also Published As

Publication number Publication date
JP3908618B2 (ja) 2007-04-25
US20040098630A1 (en) 2004-05-20
EP1271290A2 (de) 2003-01-02
JP2003224467A (ja) 2003-08-08
US6668357B2 (en) 2003-12-23
EP1271290B1 (de) 2009-11-11
EP1271290A3 (de) 2006-10-04
US7051294B2 (en) 2006-05-23
US20030034800A1 (en) 2003-02-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE