DE60209892D1 - Synchroner empfänger mit digital gesteuerter phasenschiebeeinheit (dll) und takterkennung - Google Patents

Synchroner empfänger mit digital gesteuerter phasenschiebeeinheit (dll) und takterkennung

Info

Publication number
DE60209892D1
DE60209892D1 DE60209892T DE60209892T DE60209892D1 DE 60209892 D1 DE60209892 D1 DE 60209892D1 DE 60209892 T DE60209892 T DE 60209892T DE 60209892 T DE60209892 T DE 60209892T DE 60209892 D1 DE60209892 D1 DE 60209892D1
Authority
DE
Germany
Prior art keywords
clock
source synchronous
synchronous receiver
receiver
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60209892T
Other languages
English (en)
Inventor
Wai Fong
Jyh-Ming Jong
Leo Yuan
Brian Smith
Prabhansu Chakrabarti
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60209892D1 publication Critical patent/DE60209892D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Networks Using Active Elements (AREA)
DE60209892T 2001-04-24 2002-04-22 Synchroner empfänger mit digital gesteuerter phasenschiebeeinheit (dll) und takterkennung Expired - Fee Related DE60209892D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/842,332 US6937680B2 (en) 2001-04-24 2001-04-24 Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection
PCT/US2002/012713 WO2002086687A1 (en) 2001-04-24 2002-04-22 Synchronous receiver with digital locked loop (dll) and clock detection

Publications (1)

Publication Number Publication Date
DE60209892D1 true DE60209892D1 (de) 2006-05-11

Family

ID=25287082

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60209892T Expired - Fee Related DE60209892D1 (de) 2001-04-24 2002-04-22 Synchroner empfänger mit digital gesteuerter phasenschiebeeinheit (dll) und takterkennung

Country Status (7)

Country Link
US (1) US6937680B2 (de)
EP (1) EP1381930B1 (de)
JP (1) JP2004520649A (de)
KR (1) KR20030016281A (de)
AT (1) ATE320626T1 (de)
DE (1) DE60209892D1 (de)
WO (1) WO2002086687A1 (de)

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US7194053B2 (en) * 2001-12-18 2007-03-20 Avago Technologies General Ip (Singapore) Pte. Ltd. System and method for matching data and clock signal delays to improve setup and hold times
EP1333350A1 (de) * 2002-01-30 2003-08-06 STMicroelectronics Limited Speichersicherungseinrichtung
US7127536B2 (en) * 2002-09-30 2006-10-24 Hewlett-Packard Development Company, L.P. Source-synchronous receiver having a predetermined data receive time
US7313210B2 (en) * 2003-02-28 2007-12-25 Hewlett-Packard Development Company, L.P. System and method for establishing a known timing relationship between two clock signals
US7366935B1 (en) 2003-04-01 2008-04-29 Extreme Networks, Inc. High speed bus with alignment, re-timing and buffer underflow/overflow detection enhancements
US7272672B1 (en) 2003-04-01 2007-09-18 Extreme Networks, Inc. High speed bus with flow control and extended burst enhancements between sender and receiver wherein counter is maintained at sender for free buffer space available
US7356618B2 (en) * 2003-12-31 2008-04-08 Intel Corporation Method and system for synchronizing platform clocks in a distributed wireless platform
US7197658B2 (en) * 2003-12-31 2007-03-27 Intel Corporation Synchronizing samples of a multimedia stream with a system clock
US7266713B2 (en) * 2004-01-09 2007-09-04 Intel Corporation Apparatus and method for adaptation of time synchronization of a plurality of multimedia streams
KR100605588B1 (ko) * 2004-03-05 2006-07-28 주식회사 하이닉스반도체 반도체 기억 소자에서의 지연 고정 루프 및 그의 클럭록킹 방법
US7656906B2 (en) * 2005-01-21 2010-02-02 Hewlett-Packard Development Company, L.P. System and method for communicating a timing signal between backplanes
KR100639230B1 (ko) * 2005-06-30 2006-10-30 주식회사 하이닉스반도체 출력 드라이버 제어 장치를 갖는 동기식 메모리 장치
US7555085B1 (en) 2005-08-23 2009-06-30 Sun Microsystems, Inc. CDR algorithms for improved high speed IO performance
KR100810070B1 (ko) 2005-09-29 2008-03-06 주식회사 하이닉스반도체 지연고정루프
KR100804154B1 (ko) * 2005-09-29 2008-02-19 주식회사 하이닉스반도체 지연고정루프회로
US7449930B2 (en) 2005-09-29 2008-11-11 Hynix Semiconductor Inc. Delay locked loop circuit
JP4534162B2 (ja) * 2006-05-30 2010-09-01 エルピーダメモリ株式会社 半導体集積回路装置
US7636408B2 (en) * 2006-06-01 2009-12-22 Sun Microsystems, Inc. Reliable startup and steady-state of estimation based CDR and DFE
US8416761B2 (en) 2006-09-28 2013-04-09 Motorola Mobility Llc Mitigating synchronization loss
US7626436B2 (en) * 2007-02-12 2009-12-01 Standard Microsystems Corporation Automatic system clock detection system
CN101617371B (zh) * 2007-02-16 2014-03-26 莫塞德技术公司 具有多个外部电源的非易失性半导体存储器
US8781053B2 (en) * 2007-12-14 2014-07-15 Conversant Intellectual Property Management Incorporated Clock reproducing and timing method in a system having a plurality of devices
US8467486B2 (en) * 2007-12-14 2013-06-18 Mosaid Technologies Incorporated Memory controller with flexible data alignment to clock
KR101022674B1 (ko) 2008-12-05 2011-03-22 주식회사 하이닉스반도체 지연고정루프회로 및 그 동작방법
US8218702B2 (en) * 2009-02-18 2012-07-10 Oracle America, Inc. System and method of adapting precursor tap coefficient
US8229020B2 (en) * 2009-03-23 2012-07-24 Oracle America, Inc. Integrated equalization and CDR adaptation engine with single error monitor circuit
US8488657B2 (en) * 2010-06-04 2013-07-16 Maxim Integrated Products, Inc. Data interface with delay locked loop for high speed digital to analog converters and analog to digital converters
US8976163B2 (en) 2012-06-07 2015-03-10 Apple Inc. Using clock detect circuitry to reduce panel turn-on time
JP5993665B2 (ja) * 2012-08-31 2016-09-14 ローム株式会社 シリアルデータの受信回路および受信方法、オーディオ信号処理回路、電子機器、オーディオシステム
US10944407B1 (en) 2020-06-03 2021-03-09 Stmicroelectronics International N.V. Source synchronous interface with selectable delay on source and delay on destination control

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US5774001A (en) * 1995-12-20 1998-06-30 Intel Corporation Method for eliminating multiple output switching timing skews in a source synchronous design
JP2924773B2 (ja) 1996-03-28 1999-07-26 日本電気株式会社 位相同期システム
US5886582A (en) 1996-08-07 1999-03-23 Cypress Semiconductor Corp. Enabling clock signals with a phase locked loop (PLL) lock detect circuit
JP3717289B2 (ja) 1997-10-20 2005-11-16 富士通株式会社 集積回路装置
US6178206B1 (en) 1998-01-26 2001-01-23 Intel Corporation Method and apparatus for source synchronous data transfer
US6016066A (en) 1998-03-19 2000-01-18 Intel Corporation Method and apparatus for glitch protection for input buffers in a source-synchronous environment
US6209069B1 (en) * 1998-05-11 2001-03-27 Intel Corporation Method and apparatus using volatile lock architecture for individual block locking on flash memory
JP3993717B2 (ja) 1998-09-24 2007-10-17 富士通株式会社 半導体集積回路装置
JP3973308B2 (ja) * 1998-11-27 2007-09-12 富士通株式会社 セルフタイミング制御回路を内蔵する集積回路装置
US6131168A (en) 1999-03-18 2000-10-10 Agilent Technologies System and method for reducing phase error in clocks produced by a delay locked loop
US6233200B1 (en) * 1999-12-15 2001-05-15 Intel Corporation Method and apparatus for selectively disabling clock distribution

Also Published As

Publication number Publication date
US6937680B2 (en) 2005-08-30
KR20030016281A (ko) 2003-02-26
WO2002086687A1 (en) 2002-10-31
EP1381930B1 (de) 2006-03-15
EP1381930A1 (de) 2004-01-21
US20020154718A1 (en) 2002-10-24
JP2004520649A (ja) 2004-07-08
ATE320626T1 (de) 2006-04-15

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee