DE60203477D1 - Architektur eines Flash-EEPROMs, der gleichzeitig während des Löschens oder Programmierens von einem oder mehreren anderen Sektoren, lesbar ist. - Google Patents

Architektur eines Flash-EEPROMs, der gleichzeitig während des Löschens oder Programmierens von einem oder mehreren anderen Sektoren, lesbar ist.

Info

Publication number
DE60203477D1
DE60203477D1 DE60203477T DE60203477T DE60203477D1 DE 60203477 D1 DE60203477 D1 DE 60203477D1 DE 60203477 T DE60203477 T DE 60203477T DE 60203477 T DE60203477 T DE 60203477T DE 60203477 D1 DE60203477 D1 DE 60203477D1
Authority
DE
Germany
Prior art keywords
sectors
programming
architecture
flash eeprom
during erasure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60203477T
Other languages
English (en)
Inventor
Andrea Silvagni
Rino Micheloni
Giovanni Campardo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60203477D1 publication Critical patent/DE60203477D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously
DE60203477T 2002-01-11 2002-01-11 Architektur eines Flash-EEPROMs, der gleichzeitig während des Löschens oder Programmierens von einem oder mehreren anderen Sektoren, lesbar ist. Expired - Lifetime DE60203477D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP02425009A EP1327992B1 (de) 2002-01-11 2002-01-11 Architektur eines Flash-EEPROMs, der gleichzeitig während des Löschens oder Programmierens von einem oder mehreren anderen Sektoren, lesbar ist.

Publications (1)

Publication Number Publication Date
DE60203477D1 true DE60203477D1 (de) 2005-05-04

Family

ID=8185823

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60203477T Expired - Lifetime DE60203477D1 (de) 2002-01-11 2002-01-11 Architektur eines Flash-EEPROMs, der gleichzeitig während des Löschens oder Programmierens von einem oder mehreren anderen Sektoren, lesbar ist.

Country Status (3)

Country Link
US (1) US6891755B2 (de)
EP (1) EP1327992B1 (de)
DE (1) DE60203477D1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100476889B1 (ko) * 2002-04-04 2005-03-17 삼성전자주식회사 플래쉬메모리의 워드라인디코더
WO2005017909A1 (ja) * 2003-08-18 2005-02-24 Fujitsu Limited 不揮発性半導体メモリ
US7203129B2 (en) * 2004-02-16 2007-04-10 Taiwan Semiconductor Manufacturing Company, Ltd. Segmented MRAM memory array
KR100597636B1 (ko) 2004-06-08 2006-07-05 삼성전자주식회사 상 변화 반도체 메모리 장치
US7042765B2 (en) * 2004-08-06 2006-05-09 Freescale Semiconductor, Inc. Memory bit line segment isolation
US7149111B2 (en) * 2004-12-17 2006-12-12 Msystems Ltd. Method of handling limitations on the order of writing to a non-volatile memory
KR100688540B1 (ko) * 2005-03-24 2007-03-02 삼성전자주식회사 메모리 셀의 집적도를 향상시킨 반도체 메모리 장치
JP4836487B2 (ja) * 2005-04-28 2011-12-14 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
US7453734B2 (en) * 2006-11-01 2008-11-18 Macronix International Co., Ltd. Method and apparatus for fast programming of memory
US20080232169A1 (en) * 2007-03-20 2008-09-25 Atmel Corporation Nand-like memory array employing high-density nor-like memory devices
US8098525B2 (en) * 2007-09-17 2012-01-17 Spansion Israel Ltd Pre-charge sensing scheme for non-volatile memory (NVM)
US8120959B2 (en) * 2008-05-30 2012-02-21 Aplus Flash Technology, Inc. NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same
ITTO20080647A1 (it) * 2008-08-29 2010-02-28 St Microelectronics Srl Decodificatore di colonna per dispositivi di memoria non volatili, in particolare del tipo a cambiamento di fase
US8189390B2 (en) * 2009-03-05 2012-05-29 Mosaid Technologies Incorporated NAND flash architecture with multi-level row decoding
ITUA20161478A1 (it) * 2016-03-09 2017-09-09 St Microelectronics Srl Circuito e metodo di lettura di una cella di memoria di un dispositivo di memoria non volatile
CN105810247B (zh) * 2016-04-19 2022-11-18 兆易创新科技集团股份有限公司 一种字线驱动电路
KR102608825B1 (ko) * 2018-04-26 2023-12-04 에스케이하이닉스 주식회사 메모리 컨트롤러 및 이의 동작 방법
KR102650603B1 (ko) * 2018-07-24 2024-03-27 삼성전자주식회사 불휘발성 메모리 장치, 불휘발성 메모리 장치의 동작 방법 및 불휘발성 메모리 장치를 제어하는 메모리 컨트롤러의 동작 방법

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0745995B1 (de) * 1995-05-05 2001-04-11 STMicroelectronics S.r.l. Anordnung von nichtflüchtigen EEPROM,insbesondere Flash-EEPROM
US5847998A (en) * 1996-12-20 1998-12-08 Advanced Micro Devices, Inc. Non-volatile memory array that enables simultaneous read and write operations
US6016270A (en) * 1998-03-06 2000-01-18 Alliance Semiconductor Corporation Flash memory architecture that utilizes a time-shared address bus scheme and separate memory cell access paths for simultaneous read/write operations
US6377502B1 (en) * 1999-05-10 2002-04-23 Kabushiki Kaisha Toshiba Semiconductor device that enables simultaneous read and write/erase operation
EP1063653B1 (de) * 1999-06-24 2004-11-17 STMicroelectronics S.r.l. Nichtflüchtige Speicheranordnung, insbesondere vom Flash-Typ
US6400603B1 (en) * 2000-05-03 2002-06-04 Advanced Technology Materials, Inc. Electronically-eraseable programmable read-only memory having reduced-page-size program and erase

Also Published As

Publication number Publication date
EP1327992A1 (de) 2003-07-16
EP1327992B1 (de) 2005-03-30
US6891755B2 (en) 2005-05-10
US20030133325A1 (en) 2003-07-17

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