DE602007004879D1 - Verfahren zur herstellung eines hybridsubstrats - Google Patents
Verfahren zur herstellung eines hybridsubstratsInfo
- Publication number
- DE602007004879D1 DE602007004879D1 DE602007004879T DE602007004879T DE602007004879D1 DE 602007004879 D1 DE602007004879 D1 DE 602007004879D1 DE 602007004879 T DE602007004879 T DE 602007004879T DE 602007004879 T DE602007004879 T DE 602007004879T DE 602007004879 D1 DE602007004879 D1 DE 602007004879D1
- Authority
- DE
- Germany
- Prior art keywords
- substrate
- cavity
- formation
- block
- preparing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Physical Or Chemical Processes And Apparatus (AREA)
- Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
- Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
- Preparation Of Compounds By Using Micro-Organisms (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0655193A FR2909221B1 (fr) | 2006-11-29 | 2006-11-29 | Procede de realisation d'un substrat mixte. |
PCT/EP2007/062959 WO2008065143A1 (fr) | 2006-11-29 | 2007-11-28 | Procede de realisation d'un substrat mixte |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602007004879D1 true DE602007004879D1 (de) | 2010-04-01 |
Family
ID=38057350
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602007004879T Active DE602007004879D1 (de) | 2006-11-29 | 2007-11-28 | Verfahren zur herstellung eines hybridsubstrats |
Country Status (7)
Country | Link |
---|---|
US (1) | US20100081280A1 (de) |
EP (1) | EP2084736B1 (de) |
JP (1) | JP5431948B2 (de) |
AT (1) | ATE458271T1 (de) |
DE (1) | DE602007004879D1 (de) |
FR (1) | FR2909221B1 (de) |
WO (1) | WO2008065143A1 (de) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2156625A2 (de) * | 2007-06-05 | 2010-02-24 | InterDigital Technology Corporation | Rrc nachrichten und prozeduren |
DE102011010248B3 (de) * | 2011-02-03 | 2012-07-12 | Infineon Technologies Ag | Ein Verfahren zum Herstellen eines Halbleiterbausteins |
FR3009428B1 (fr) | 2013-08-05 | 2015-08-07 | Commissariat Energie Atomique | Procede de fabrication d'une structure semi-conductrice avec collage temporaire via des couches metalliques |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59132142A (ja) * | 1983-01-18 | 1984-07-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS6080244A (ja) * | 1983-10-07 | 1985-05-08 | Hitachi Ltd | 半導体装置の素子分離方法 |
US5292689A (en) * | 1992-09-04 | 1994-03-08 | International Business Machines Corporation | Method for planarizing semiconductor structure using subminimum features |
US5747377A (en) * | 1996-09-06 | 1998-05-05 | Powerchip Semiconductor Corp. | Process for forming shallow trench isolation |
US6599812B1 (en) * | 1998-10-23 | 2003-07-29 | Stmicroelectronics S.R.L. | Manufacturing method for a thick oxide layer |
US6793981B2 (en) * | 1999-03-23 | 2004-09-21 | Dai Nippon Printing Co., Ltd. | Process for producing laminated film, and reflection reducing film |
DE10130379A1 (de) * | 2001-06-23 | 2003-01-02 | Bosch Gmbh Robert | Mikromechanischer Massenflusssensor und Verfahren zu dessen Herstellung |
JP4161745B2 (ja) * | 2003-03-06 | 2008-10-08 | 株式会社デンソー | 光学素子およびその製造方法 |
JP2005079310A (ja) * | 2003-08-29 | 2005-03-24 | Semiconductor Leading Edge Technologies Inc | 半導体装置及びその製造方法 |
US7023069B2 (en) * | 2003-12-19 | 2006-04-04 | Third Dimension (3D) Semiconductor, Inc. | Method for forming thick dielectric regions using etched trenches |
FR2876220B1 (fr) * | 2004-10-06 | 2007-09-28 | Commissariat Energie Atomique | Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees. |
US20060244074A1 (en) * | 2005-04-29 | 2006-11-02 | Chien-Hao Chen | Hybrid-strained sidewall spacer for CMOS process |
-
2006
- 2006-11-29 FR FR0655193A patent/FR2909221B1/fr not_active Expired - Fee Related
-
2007
- 2007-11-28 JP JP2009538705A patent/JP5431948B2/ja not_active Expired - Fee Related
- 2007-11-28 DE DE602007004879T patent/DE602007004879D1/de active Active
- 2007-11-28 EP EP07847476A patent/EP2084736B1/de not_active Not-in-force
- 2007-11-28 US US12/515,021 patent/US20100081280A1/en not_active Abandoned
- 2007-11-28 WO PCT/EP2007/062959 patent/WO2008065143A1/fr active Application Filing
- 2007-11-28 AT AT07847476T patent/ATE458271T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
FR2909221B1 (fr) | 2009-04-17 |
JP2010511300A (ja) | 2010-04-08 |
EP2084736B1 (de) | 2010-02-17 |
ATE458271T1 (de) | 2010-03-15 |
FR2909221A1 (fr) | 2008-05-30 |
US20100081280A1 (en) | 2010-04-01 |
WO2008065143A1 (fr) | 2008-06-05 |
JP5431948B2 (ja) | 2014-03-05 |
EP2084736A1 (de) | 2009-08-05 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |