ATE458271T1 - Verfahren zur herstellung eines hybridsubstrats - Google Patents

Verfahren zur herstellung eines hybridsubstrats

Info

Publication number
ATE458271T1
ATE458271T1 AT07847476T AT07847476T ATE458271T1 AT E458271 T1 ATE458271 T1 AT E458271T1 AT 07847476 T AT07847476 T AT 07847476T AT 07847476 T AT07847476 T AT 07847476T AT E458271 T1 ATE458271 T1 AT E458271T1
Authority
AT
Austria
Prior art keywords
substrate
cavity
formation
producing
block
Prior art date
Application number
AT07847476T
Other languages
English (en)
Inventor
Hubert Moriceau
Sylvie Sartori
Anne-Marie Charvet
Original Assignee
Commissariat Energie Atomique
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Commissariat Energie Atomique filed Critical Commissariat Energie Atomique
Application granted granted Critical
Publication of ATE458271T1 publication Critical patent/ATE458271T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0121—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves
    • H10W10/0123—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] in regions recessed from the surface, e.g. in trenches or grooves using auxiliary pillars in the regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

Landscapes

  • Element Separation (AREA)
  • Physical Or Chemical Processes And Apparatus (AREA)
  • Preparation Of Compounds By Using Micro-Organisms (AREA)
  • Macromolecular Compounds Obtained By Forming Nitrogen-Containing Linkages In General (AREA)
  • Polymers With Sulfur, Phosphorus Or Metals In The Main Chain (AREA)
AT07847476T 2006-11-29 2007-11-28 Verfahren zur herstellung eines hybridsubstrats ATE458271T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0655193A FR2909221B1 (fr) 2006-11-29 2006-11-29 Procede de realisation d'un substrat mixte.
PCT/EP2007/062959 WO2008065143A1 (fr) 2006-11-29 2007-11-28 Procede de realisation d'un substrat mixte

Publications (1)

Publication Number Publication Date
ATE458271T1 true ATE458271T1 (de) 2010-03-15

Family

ID=38057350

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07847476T ATE458271T1 (de) 2006-11-29 2007-11-28 Verfahren zur herstellung eines hybridsubstrats

Country Status (7)

Country Link
US (1) US20100081280A1 (de)
EP (1) EP2084736B1 (de)
JP (1) JP5431948B2 (de)
AT (1) ATE458271T1 (de)
DE (1) DE602007004879D1 (de)
FR (1) FR2909221B1 (de)
WO (1) WO2008065143A1 (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008151243A2 (en) * 2007-06-05 2008-12-11 Interdigital Technology Corporation Rrc messages and procedures
DE102011010248B3 (de) * 2011-02-03 2012-07-12 Infineon Technologies Ag Ein Verfahren zum Herstellen eines Halbleiterbausteins
FR3009428B1 (fr) 2013-08-05 2015-08-07 Commissariat Energie Atomique Procede de fabrication d'une structure semi-conductrice avec collage temporaire via des couches metalliques
JP7712730B1 (ja) * 2024-12-31 2025-07-24 ＡＴＩ Ｊａｐａｎ 株式会社 酸化シリコン膜をもつシリコン基板の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59132142A (ja) * 1983-01-18 1984-07-30 Mitsubishi Electric Corp 半導体装置の製造方法
JPS6080244A (ja) * 1983-10-07 1985-05-08 Hitachi Ltd 半導体装置の素子分離方法
US5292689A (en) * 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
US5747377A (en) * 1996-09-06 1998-05-05 Powerchip Semiconductor Corp. Process for forming shallow trench isolation
US6599812B1 (en) * 1998-10-23 2003-07-29 Stmicroelectronics S.R.L. Manufacturing method for a thick oxide layer
US6793981B2 (en) * 1999-03-23 2004-09-21 Dai Nippon Printing Co., Ltd. Process for producing laminated film, and reflection reducing film
DE10130379A1 (de) * 2001-06-23 2003-01-02 Bosch Gmbh Robert Mikromechanischer Massenflusssensor und Verfahren zu dessen Herstellung
JP4161745B2 (ja) * 2003-03-06 2008-10-08 株式会社デンソー 光学素子およびその製造方法
JP2005079310A (ja) * 2003-08-29 2005-03-24 Semiconductor Leading Edge Technologies Inc 半導体装置及びその製造方法
US7023069B2 (en) * 2003-12-19 2006-04-04 Third Dimension (3D) Semiconductor, Inc. Method for forming thick dielectric regions using etched trenches
FR2876220B1 (fr) * 2004-10-06 2007-09-28 Commissariat Energie Atomique Procede d'elaboration de structures empilees mixtes, a zones isolantes diverses et/ou zones de conduction electrique verticale localisees.
US20060244074A1 (en) * 2005-04-29 2006-11-02 Chien-Hao Chen Hybrid-strained sidewall spacer for CMOS process

Also Published As

Publication number Publication date
US20100081280A1 (en) 2010-04-01
WO2008065143A1 (fr) 2008-06-05
DE602007004879D1 (de) 2010-04-01
JP5431948B2 (ja) 2014-03-05
EP2084736A1 (de) 2009-08-05
FR2909221B1 (fr) 2009-04-17
JP2010511300A (ja) 2010-04-08
FR2909221A1 (fr) 2008-05-30
EP2084736B1 (de) 2010-02-17

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