DE602007004839D1 - Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen - Google Patents

Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen

Info

Publication number
DE602007004839D1
DE602007004839D1 DE602007004839T DE602007004839T DE602007004839D1 DE 602007004839 D1 DE602007004839 D1 DE 602007004839D1 DE 602007004839 T DE602007004839 T DE 602007004839T DE 602007004839 T DE602007004839 T DE 602007004839T DE 602007004839 D1 DE602007004839 D1 DE 602007004839D1
Authority
DE
Germany
Prior art keywords
layer
conductivity type
isolation trench
integrated semiconductor
semiconductor devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007004839T
Other languages
English (en)
Inventor
Filip Bauwens
Joris Baele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Publication of DE602007004839D1 publication Critical patent/DE602007004839D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
DE602007004839T 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen Active DE602007004839D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP07012746A EP2009686B1 (de) 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen

Publications (1)

Publication Number Publication Date
DE602007004839D1 true DE602007004839D1 (de) 2010-04-01

Family

ID=38604852

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007004839T Active DE602007004839D1 (de) 2007-06-29 2007-06-29 Tiefgrabenisolationsstrukturen in integrierten Halbleiterbauelementen

Country Status (4)

Country Link
US (1) US8115273B2 (de)
EP (1) EP2009686B1 (de)
AT (1) ATE458274T1 (de)
DE (1) DE602007004839D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007129085A (ja) * 2005-11-04 2007-05-24 Texas Instr Japan Ltd 半導体装置及びその製造方法
JP5010660B2 (ja) * 2009-09-25 2012-08-29 株式会社東芝 半導体装置およびその製造方法
US8673723B1 (en) 2013-02-07 2014-03-18 Globalfoundries Inc. Methods of forming isolation regions for FinFET semiconductor devices
US9696736B2 (en) 2013-03-15 2017-07-04 Fairchild Semiconductor Corporation Two-terminal current limiter and apparatus thereof
US9679890B2 (en) * 2013-08-09 2017-06-13 Fairchild Semiconductor Corporation Junction-less insulated gate current limiter device
US9735147B2 (en) 2014-09-15 2017-08-15 Fairchild Semiconductor Corporation Fast and stable ultra low drop-out (LDO) voltage clamp device
US20170373142A1 (en) * 2016-06-23 2017-12-28 Littelfuse, Inc. Semiconductor device having side-diffused trench plug
US10607880B2 (en) * 2018-08-30 2020-03-31 Nxp Usa, Inc. Die with buried doped isolation region

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4534826A (en) * 1983-12-29 1985-08-13 Ibm Corporation Trench etch process for dielectric isolation
JP3360970B2 (ja) * 1995-05-22 2003-01-07 株式会社東芝 半導体装置の製造方法
US6734524B1 (en) * 2002-12-31 2004-05-11 Motorola, Inc. Electronic component and method of manufacturing same
US7491618B2 (en) * 2006-01-26 2009-02-17 International Business Machines Corporation Methods and semiconductor structures for latch-up suppression using a conductive region

Also Published As

Publication number Publication date
US20090039460A1 (en) 2009-02-12
ATE458274T1 (de) 2010-03-15
EP2009686B1 (de) 2010-02-17
US8115273B2 (en) 2012-02-14
EP2009686A1 (de) 2008-12-31

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Legal Events

Date Code Title Description
8381 Inventor (new situation)

Inventor name: BAELE, JORIS, 9000 GENT, BE

Inventor name: MOENS, PETER, ZOTTGEM, BE

Inventor name: BAUWENS, FILIP, 8210 LOPPEM, BE

8364 No opposition during term of opposition