DE602006018075D1 - Einrichtung und verfahren zum prüfen integrierter schaltungen - Google Patents

Einrichtung und verfahren zum prüfen integrierter schaltungen

Info

Publication number
DE602006018075D1
DE602006018075D1 DE602006018075T DE602006018075T DE602006018075D1 DE 602006018075 D1 DE602006018075 D1 DE 602006018075D1 DE 602006018075 T DE602006018075 T DE 602006018075T DE 602006018075 T DE602006018075 T DE 602006018075T DE 602006018075 D1 DE602006018075 D1 DE 602006018075D1
Authority
DE
Germany
Prior art keywords
integrated circuits
checking integrated
checking
circuits
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006018075T
Other languages
English (en)
Inventor
Ezra Baruch
Michael Priel
Dan Kuzmin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of DE602006018075D1 publication Critical patent/DE602006018075D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31703—Comparison aspects, e.g. signature analysis, comparators
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318522—Test of Sequential circuits
    • G01R31/318525—Test of flip-flops or latches

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE602006018075T 2006-05-29 2006-05-29 Einrichtung und verfahren zum prüfen integrierter schaltungen Active DE602006018075D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/IB2006/051700 WO2007138387A1 (en) 2006-05-29 2006-05-29 Device and method for testing integrated circuits

Publications (1)

Publication Number Publication Date
DE602006018075D1 true DE602006018075D1 (de) 2010-12-16

Family

ID=37684955

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006018075T Active DE602006018075D1 (de) 2006-05-29 2006-05-29 Einrichtung und verfahren zum prüfen integrierter schaltungen

Country Status (5)

Country Link
US (1) US8030953B2 (de)
EP (1) EP2030030B1 (de)
JP (1) JP5166408B2 (de)
DE (1) DE602006018075D1 (de)
WO (1) WO2007138387A1 (de)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4244048A (en) * 1978-12-29 1981-01-06 International Business Machines Corporation Chip and wafer configuration and testing method for large-scale-integrated circuits
JPH02146199A (ja) * 1988-11-28 1990-06-05 Mitsubishi Electric Corp 半導体記憶装置のテスト回路
JP2001266599A (ja) * 2000-03-17 2001-09-28 Nec Microsystems Ltd 半導体記憶装置の試験方法および試験装置
US6829737B1 (en) * 2000-08-30 2004-12-07 Micron Technology, Inc. Method and system for storing device test information on a semiconductor device using on-device logic for determination of test results
JP5030336B2 (ja) * 2001-06-07 2012-09-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US6989702B2 (en) * 2002-07-11 2006-01-24 Texas Instruments Incorporated Retention register with normal functionality independent of retention power supply
JP2005050393A (ja) * 2003-07-29 2005-02-24 Toshiba Lsi System Support Kk 半導体装置およびその故障検出方法

Also Published As

Publication number Publication date
JP2009539094A (ja) 2009-11-12
US20090195265A1 (en) 2009-08-06
EP2030030B1 (de) 2010-11-03
EP2030030A1 (de) 2009-03-04
US8030953B2 (en) 2011-10-04
WO2007138387A1 (en) 2007-12-06
JP5166408B2 (ja) 2013-03-21

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