DE602006016388D1 - Eine teilbare Nachschlagstabelle für flächeneffiziente logische Elemente - Google Patents

Eine teilbare Nachschlagstabelle für flächeneffiziente logische Elemente

Info

Publication number
DE602006016388D1
DE602006016388D1 DE602006016388T DE602006016388T DE602006016388D1 DE 602006016388 D1 DE602006016388 D1 DE 602006016388D1 DE 602006016388 T DE602006016388 T DE 602006016388T DE 602006016388 T DE602006016388 T DE 602006016388T DE 602006016388 D1 DE602006016388 D1 DE 602006016388D1
Authority
DE
Germany
Prior art keywords
divisible
look
area
logical elements
efficient logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006016388T
Other languages
English (en)
Inventor
Sinan Kaptanoglu
Bruce B Pedersen
James G Schleicher
Jinyong Yuan
Michael D Hutton
David Lewis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of DE602006016388D1 publication Critical patent/DE602006016388D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
DE602006016388T 2005-09-22 2006-09-21 Eine teilbare Nachschlagstabelle für flächeneffiziente logische Elemente Active DE602006016388D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/234,538 US7330052B2 (en) 2005-09-22 2005-09-22 Area efficient fractureable logic elements

Publications (1)

Publication Number Publication Date
DE602006016388D1 true DE602006016388D1 (de) 2010-10-07

Family

ID=37492422

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006016388T Active DE602006016388D1 (de) 2005-09-22 2006-09-21 Eine teilbare Nachschlagstabelle für flächeneffiziente logische Elemente

Country Status (5)

Country Link
US (1) US7330052B2 (de)
EP (1) EP1770865B1 (de)
JP (1) JP5026037B2 (de)
CN (1) CN1937409B (de)
DE (1) DE602006016388D1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7902864B1 (en) * 2005-12-01 2011-03-08 Altera Corporation Heterogeneous labs
US7812633B1 (en) * 2006-04-03 2010-10-12 Altera Corporation Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device
US7812635B1 (en) 2006-05-08 2010-10-12 Altera Corporation Programmable logic device architecture with the ability to combine adjacent logic elements for the purpose of performing high order logic functions
US7394287B1 (en) * 2007-05-21 2008-07-01 Altera Corporation Programmable logic device having complex logic blocks with improved logic cell functionality
US7459932B1 (en) * 2007-05-24 2008-12-02 Altera Corporation Programmable logic device having logic modules with improved register capabilities
JP5360194B2 (ja) * 2009-03-18 2013-12-04 日本電気株式会社 再構成可能な論理回路
JP5618275B2 (ja) * 2011-06-12 2014-11-05 独立行政法人産業技術総合研究所 Ｃｍｏｓインバータを用いたマルチプレクサ、デマルチプレクサ、ルックアップテーブルおよび集積回路
US8519740B2 (en) 2012-01-06 2013-08-27 Altera Corporation Integrated circuits with shared interconnect buses
CN103259528A (zh) * 2012-02-17 2013-08-21 京微雅格（北京）科技有限公司 一种异构可编程逻辑结构的集成电路
US8581624B2 (en) 2012-03-29 2013-11-12 Altera Corporation Integrated circuits with multi-stage logic regions
US9571103B2 (en) 2012-05-25 2017-02-14 Semiconductor Energy Laboratory Co., Ltd. Lookup table and programmable logic device including lookup table
KR102125593B1 (ko) * 2013-02-13 2020-06-22 가부시키가이샤 한도오따이 에네루기 켄큐쇼 프로그래머블 로직 디바이스 및 반도체 장치
WO2015051105A1 (en) * 2013-10-02 2015-04-09 The Penn State Research Foundation Techniques and devices for performing arithmetic
CN103762974B (zh) * 2014-01-26 2016-09-14 无锡中微亿芯有限公司 多功能可配置的六输入查找表结构
EP3157171B1 (de) * 2015-10-15 2020-06-03 Menta Logische blockarchitektur für ein programmierbares gate-array
US10312918B2 (en) * 2017-02-13 2019-06-04 High Performance Data Storage And Processing Corporation Programmable logic design
US10530397B2 (en) * 2017-07-17 2020-01-07 Texas Instruments Incorporated Butterfly network on load data return
US11256476B2 (en) 2019-08-08 2022-02-22 Achronix Semiconductor Corporation Multiple mode arithmetic circuit

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3580785B2 (ja) * 2001-06-29 2004-10-27 株式会社半導体理工学研究センター ルックアップテーブル、ルックアップテーブルを備えるプログラマブル論理回路装置、および、ルックアップテーブルの構成方法
US6747480B1 (en) 2002-07-12 2004-06-08 Altera Corporation Programmable logic devices with bidirect ional cascades
US6798240B1 (en) 2003-01-24 2004-09-28 Altera Corporation Logic circuitry with shared lookup table
US6943580B2 (en) 2003-02-10 2005-09-13 Altera Corporation Fracturable lookup table and logic element
US6888373B2 (en) * 2003-02-11 2005-05-03 Altera Corporation Fracturable incomplete look up table for area efficient logic elements
US7185035B1 (en) * 2003-10-23 2007-02-27 Altera Corporation Arithmetic structures for programmable logic devices
US7176716B2 (en) * 2003-12-24 2007-02-13 Viciciv Technology Look-up table structure with embedded carry logic
US7167022B1 (en) * 2004-03-25 2007-01-23 Altera Corporation Omnibus logic element including look up table based logic elements

Also Published As

Publication number Publication date
US7330052B2 (en) 2008-02-12
JP5026037B2 (ja) 2012-09-12
CN1937409A (zh) 2007-03-28
EP1770865A1 (de) 2007-04-04
EP1770865B1 (de) 2010-08-25
JP2007089180A (ja) 2007-04-05
US20070063732A1 (en) 2007-03-22
CN1937409B (zh) 2012-01-25

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