DE602006013282D1 - Verfahren und system zur terminplanung von tests in einem parallelen testsystem - Google Patents

Verfahren und system zur terminplanung von tests in einem parallelen testsystem

Info

Publication number
DE602006013282D1
DE602006013282D1 DE602006013282T DE602006013282T DE602006013282D1 DE 602006013282 D1 DE602006013282 D1 DE 602006013282D1 DE 602006013282 T DE602006013282 T DE 602006013282T DE 602006013282 T DE602006013282 T DE 602006013282T DE 602006013282 D1 DE602006013282 D1 DE 602006013282D1
Authority
DE
Germany
Prior art keywords
terminating
tests
parallel test
test system
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006013282T
Other languages
English (en)
Inventor
Ankan Pramanick
Toshiaki Adachi
Mark Elston
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of DE602006013282D1 publication Critical patent/DE602006013282D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31912—Tester/user interface

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Tests Of Electronic Circuits (AREA)
DE602006013282T 2005-02-17 2006-02-17 Verfahren und system zur terminplanung von tests in einem parallelen testsystem Active DE602006013282D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/062,244 US7543200B2 (en) 2005-02-17 2005-02-17 Method and system for scheduling tests in a parallel test system
PCT/JP2006/303337 WO2006088238A1 (en) 2005-02-17 2006-02-17 Method and system for scheduling tests in a parallel test system

Publications (1)

Publication Number Publication Date
DE602006013282D1 true DE602006013282D1 (de) 2010-05-12

Family

ID=36604219

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006013282T Active DE602006013282D1 (de) 2005-02-17 2006-02-17 Verfahren und system zur terminplanung von tests in einem parallelen testsystem

Country Status (8)

Country Link
US (1) US7543200B2 (de)
EP (1) EP1849019B1 (de)
JP (1) JP2008530515A (de)
KR (1) KR20070112203A (de)
CN (1) CN101120262B (de)
DE (1) DE602006013282D1 (de)
TW (1) TWI385405B (de)
WO (1) WO2006088238A1 (de)

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7543200B2 (en) 2005-02-17 2009-06-02 Advantest Corporation Method and system for scheduling tests in a parallel test system
JP4370274B2 (ja) * 2005-03-14 2009-11-25 富士通株式会社 検証支援装置、検証支援方法、および検証支援プログラム
US7650255B2 (en) * 2008-05-02 2010-01-19 Texas Instruments Incorporated Automatic selective retest for multi-site testers
US7853425B1 (en) * 2008-07-11 2010-12-14 Keithley Instruments, Inc. Parallel testing in a per-pin hardware architecture platform
TWI461712B (zh) * 2009-01-21 2014-11-21 King Yuan Electronics Co Ltd 平行測試轉換裝置、平行測試系統以及平行測試之方法
US20130006567A1 (en) * 2009-12-15 2013-01-03 Wolfgang Horn Method and apparatus for scheduling a use of test resources of a test arrangement for the execution of test groups
KR101742590B1 (ko) * 2010-05-05 2017-06-01 테라다인 인코퍼레이티드 반도체 장치들의 동시 시험을 위한 시스템
US20110288808A1 (en) * 2010-05-20 2011-11-24 International Business Machines Corporation Optimal test flow scheduling within automated test equipment for minimized mean time to detect failure
US8175213B2 (en) 2010-07-28 2012-05-08 Freescale Semiconductor, Inc. System and method for setting counter threshold value
US20120102462A1 (en) * 2010-10-26 2012-04-26 Microsoft Corporation Parallel test execution
KR101734364B1 (ko) * 2010-12-13 2017-05-12 삼성전자 주식회사 반도체 장치 동시 연속 테스트 방법 및 테스트 장비
TWI412773B (zh) * 2011-06-27 2013-10-21 Powertech Technology Inc 多驅動器交叉連接之記憶體測試裝置及其使用方法
JP5841457B2 (ja) * 2012-03-01 2016-01-13 株式会社アドバンテスト 試験装置および試験モジュール
US8867372B2 (en) * 2012-05-02 2014-10-21 Litepoint Corporation Method for efficient parallel testing of time division duplex (TDD) communications systems
CN102722170B (zh) * 2012-05-10 2014-08-27 北京宇航系统工程研究所 一种用于运载火箭测试发射阶段的故障检测方法
CN102998613A (zh) * 2012-11-26 2013-03-27 李文海 可实现电路板并行测试的测试系统和方法
US9158642B2 (en) * 2012-12-20 2015-10-13 Litepoint Corporation Method of testing multiple data packet signal transceivers concurrently
US9207969B2 (en) 2013-01-25 2015-12-08 Microsoft Technology Licensing, Llc Parallel tracing for performance and detail
US9021262B2 (en) 2013-01-25 2015-04-28 Concurix Corporation Obfuscating trace data
US8954546B2 (en) 2013-01-25 2015-02-10 Concurix Corporation Tracing with a workload distributor
US8997063B2 (en) 2013-02-12 2015-03-31 Concurix Corporation Periodicity optimization in an automated tracing system
US20130283281A1 (en) 2013-02-12 2013-10-24 Concurix Corporation Deploying Trace Objectives using Cost Analyses
US8924941B2 (en) 2013-02-12 2014-12-30 Concurix Corporation Optimization analysis using similar frequencies
US9274911B2 (en) * 2013-02-21 2016-03-01 Advantest Corporation Using shared pins in a concurrent test execution environment
US20140236527A1 (en) * 2013-02-21 2014-08-21 Advantest Corporation Cloud based infrastructure for supporting protocol reconfigurations in protocol independent device testing systems
US10161993B2 (en) * 2013-02-21 2018-12-25 Advantest Corporation Tester with acceleration on memory and acceleration for automatic pattern generation within a FPGA block
US10162007B2 (en) * 2013-02-21 2018-12-25 Advantest Corporation Test architecture having multiple FPGA based hardware accelerator blocks for testing multiple DUTs independently
US9400307B2 (en) 2013-03-13 2016-07-26 Keysight Technologies, Inc. Test system for improving throughout or maintenance properties of semiconductor testing
US9665474B2 (en) 2013-03-15 2017-05-30 Microsoft Technology Licensing, Llc Relationships derived from trace data
US9785542B2 (en) * 2013-04-16 2017-10-10 Advantest Corporation Implementing edit and update functionality within a development environment used to compile test plans for automated semiconductor device testing
US9575874B2 (en) 2013-04-20 2017-02-21 Microsoft Technology Licensing, Llc Error list and bug report analysis for configuring an application tracer
US9292415B2 (en) 2013-09-04 2016-03-22 Microsoft Technology Licensing, Llc Module specific tracing in a shared module environment
US9772927B2 (en) 2013-11-13 2017-09-26 Microsoft Technology Licensing, Llc User interface for selecting tracing origins for aggregating classes of trace data
CN104931086A (zh) * 2014-03-18 2015-09-23 光宝电子(广州)有限公司 平行多工测试系统及测试方法
US9298590B2 (en) * 2014-06-26 2016-03-29 Google Inc. Methods and apparatuses for automated testing of streaming applications using mapreduce-like middleware
US9727447B1 (en) * 2015-01-16 2017-08-08 Amdocs Software Systems Limited System, method, and computer program for automated exploratory testing
CN104635092A (zh) * 2015-02-26 2015-05-20 北京精密机电控制设备研究所 机电伺服系统检测装置及检测方法
WO2016155830A1 (en) 2015-04-01 2016-10-06 Advantest Corporation Method for operating a test apparatus and a test apparatus
US9804911B2 (en) 2015-05-27 2017-10-31 Apple Inc. Concurrent validation of hardware units
CN105117348A (zh) * 2015-09-28 2015-12-02 佛山市朗达信息科技有限公司 一种监控软件测试执行进度的方法
US10725800B2 (en) 2015-10-16 2020-07-28 Dell Products L.P. User-specific customization for command interface
US10748116B2 (en) * 2015-10-16 2020-08-18 Dell Products L.P. Test vector generation from documentation
US10608879B2 (en) 2015-10-16 2020-03-31 Dell Products L.P. Validation using natural language processing
WO2017129242A1 (en) * 2016-01-27 2017-08-03 Advantest Corporation Deterministic concurrent test program executor for an automated test equipment
US10181224B2 (en) 2016-03-17 2019-01-15 Accenture Global Solutions Limited Assigning a test suite to test equipment using an execution graph
US10241146B2 (en) * 2017-05-01 2019-03-26 Advantest Corporation Test system and method
TWI653519B (zh) * 2017-05-03 2019-03-11 和碩聯合科技股份有限公司 配置單元、檢測系統及檢測方法
CN109375965B (zh) * 2018-11-06 2022-04-26 东软集团股份有限公司 状态机处理方法及装置、可读存储介质
US10976361B2 (en) 2018-12-20 2021-04-13 Advantest Corporation Automated test equipment (ATE) support framework for solid state device (SSD) odd sector sizes and protection modes
US11137910B2 (en) 2019-03-04 2021-10-05 Advantest Corporation Fast address to sector number/offset translation to support odd sector size testing
US11237202B2 (en) 2019-03-12 2022-02-01 Advantest Corporation Non-standard sector size system support for SSD testing
US10884847B1 (en) 2019-08-20 2021-01-05 Advantest Corporation Fast parallel CRC determination to support SSD testing
US11132403B2 (en) 2019-09-06 2021-09-28 Digital Asset Capital, Inc. Graph-manipulation based domain-specific execution environment
US10990879B2 (en) 2019-09-06 2021-04-27 Digital Asset Capital, Inc. Graph expansion and outcome determination for graph-defined program states
CN110716126A (zh) * 2019-10-14 2020-01-21 珠海亿智电子科技有限公司 芯片老化测试系统、方法及装置
CN111124642A (zh) * 2019-12-16 2020-05-08 中国电子科技网络信息安全有限公司 一种云管理平台可自定义的自动化流程方法及系统
CN111193561B (zh) * 2019-12-25 2022-07-05 深圳创维数字技术有限公司 一种双频wifi测试方法、系统、服务器和存储介质
TWI773140B (zh) * 2020-03-05 2022-08-01 日商愛德萬測試股份有限公司 用於流量捕獲及除錯工具之圖形使用者介面
CN116300836B (zh) * 2023-05-19 2023-07-28 西安诚安测控科技有限公司 发动机控制系统的测试方法和装置

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4894829A (en) 1988-04-21 1990-01-16 Honeywell Inc. Comprehensive design and maintenance environment for test program sets
EP0347162A3 (de) * 1988-06-14 1990-09-12 Tektronix, Inc. Einrichtung und Verfahren zum Steuern von Datenflussprozessen durch erzeugte Befehlsfolgen
US5701480A (en) * 1991-10-17 1997-12-23 Digital Equipment Corporation Distributed multi-version commitment ordering protocols for guaranteeing serializability during transaction processing
US5297150A (en) * 1992-06-17 1994-03-22 International Business Machines Corporation Rule-based method for testing of programming segments
US5513118A (en) * 1993-08-25 1996-04-30 Nec Usa, Inc. High level synthesis for partial scan testing
JP3158395B2 (ja) 1995-08-22 2001-04-23 横河電機株式会社 テスト実行フロー作成装置
US6061507A (en) * 1996-12-13 2000-05-09 Texas Instruments Incorporated Scheduling diagnostic testing of automated equipment for testing integrated circuit devices
JP3357577B2 (ja) * 1997-07-24 2002-12-16 富士通株式会社 故障シミュレーション方法および装置並びに故障シミュレーションプログラムを格納した記憶媒体
US6499121B1 (en) * 1999-03-01 2002-12-24 Formfactor, Inc. Distributed interface for parallel testing of multiple devices using a single tester channel
US6415396B1 (en) * 1999-03-26 2002-07-02 Lucent Technologies Inc. Automatic generation and maintenance of regression test cases from requirements
JP4251707B2 (ja) * 1999-04-02 2009-04-08 株式会社アドバンテスト 半導体デバイス試験装置及び試験方法
US6691079B1 (en) * 1999-05-28 2004-02-10 Ming-Chih Lai Method and system for analyzing test coverage
US6476628B1 (en) * 1999-06-28 2002-11-05 Teradyne, Inc. Semiconductor parallel tester
US6557128B1 (en) * 1999-11-12 2003-04-29 Advantest Corp. Semiconductor test system supporting multiple virtual logic testers
US6732304B1 (en) * 2000-09-21 2004-05-04 Inapac Technology, Inc. Chip testing within a multi-chip semiconductor package
AU2001296891A1 (en) * 2000-09-22 2002-04-02 Don Mccord Method and system for wafer and device-level testing of an integrated circuit
US6868513B1 (en) * 2000-10-26 2005-03-15 International Business Machines Corporation Automated multi-device test process and system
US20040015846A1 (en) * 2001-04-04 2004-01-22 Jupiter Controller, Inc. System, device and method for integrating functioning of autonomous processing modules, and testing apparatus using same
CN1293387C (zh) * 2001-05-11 2007-01-03 株式会社鼎新 支持多虚拟逻辑测试仪的半导体测试系统
US6779140B2 (en) * 2001-06-29 2004-08-17 Agilent Technologies, Inc. Algorithmically programmable memory tester with test sites operating in a slave mode
US6988232B2 (en) * 2001-07-05 2006-01-17 Intellitech Corporation Method and apparatus for optimized parallel testing and access of electronic circuits
US7035755B2 (en) * 2001-08-17 2006-04-25 Credence Systems Corporation Circuit testing with ring-connected test instrument modules
US7437261B2 (en) 2003-02-14 2008-10-14 Advantest Corporation Method and apparatus for testing integrated circuits
TWI344595B (en) 2003-02-14 2011-07-01 Advantest Corp Method and structure to develop a test program for semiconductor integrated circuits
JP4124345B2 (ja) * 2003-05-30 2008-07-23 シャープ株式会社 試験装置
KR100498509B1 (ko) * 2003-11-12 2005-07-01 삼성전자주식회사 검사시간을 단축하는 플래시 메모리 테스터 및 이를이용한 전기적 검사방법
JP2005300344A (ja) * 2004-04-12 2005-10-27 Matsushita Electric Ind Co Ltd 半導体集積回路のテストシステム
US7210087B2 (en) 2004-05-22 2007-04-24 Advantest America R&D Center, Inc. Method and system for simulating a modular test system
KR100548199B1 (ko) * 2004-07-15 2006-02-02 삼성전자주식회사 아날로그/디지털 혼합 신호 반도체 디바이스 테스트 장치
US7543200B2 (en) 2005-02-17 2009-06-02 Advantest Corporation Method and system for scheduling tests in a parallel test system

Also Published As

Publication number Publication date
KR20070112203A (ko) 2007-11-22
JP2008530515A (ja) 2008-08-07
US20060195747A1 (en) 2006-08-31
EP1849019B1 (de) 2010-03-31
WO2006088238A1 (en) 2006-08-24
CN101120262B (zh) 2010-08-25
TWI385405B (zh) 2013-02-11
US7543200B2 (en) 2009-06-02
TW200643449A (en) 2006-12-16
EP1849019A1 (de) 2007-10-31
CN101120262A (zh) 2008-02-06

Similar Documents

Publication Publication Date Title
DE602006013282D1 (de) Verfahren und system zur terminplanung von tests in einem parallelen testsystem
DE602006003274D1 (de) Vorrichtung und Verfahren zur Überprüfung von Gewinden
DE602006001379D1 (de) Vorrichtung und Verfahren zur Erfassung von Verschiebungen
DE602005005550D1 (de) Verfahren und Vorrichtung zur Ermüdungsprüfung
DE502006003636D1 (de) Verfahren und vorrichtung zur ermittlung geometrischer werte an einem gegenstand
DE112008003856A5 (de) Verfahren und Vorrichtung zur Detektion und Identifizierung von Gasen in Flugzeuginnenräumen
DE602005004068D1 (de) Vorrichtung und Verfahren zum Testen von Befestigungen für Bauteile
DE602005011934D1 (de) Vorrichtung zum Einfangen von Kügelchen und Verfahren und Vorrichtung zum Anordnen von Kügelchen
DE602006007458D1 (de) Verfahren und vorrichtung zur bohrlochfluidanalyse
DE102006033605B8 (de) Vorrichtung und Verfahren zur Bestimmung von Vertikalpositionen
ATE515905T1 (de) Verfahren und vorrichtung zur auswahl einer anforderungsgruppe für eine anforderungsbericht
DE602006012823D1 (de) Vorrichtung und verfahren zum neusynthetisieren von signalen
DE602005011398D1 (de) Verfahren und Vorrichtung zum Nachweis von Spurengasen
DE602006000614D1 (de) Vorrichtung und Verfahren zur Standortbestimmung
DE602005000993D1 (de) Verfahren und Modul zur Netzwerkanalyse
ATE525639T1 (de) Vorrichtung und verfahren zur prüfung von rippencontainern
DE602005022662D1 (de) Anordnung und Verfahren zur Detektierung von Tintenstrahldefekten
DE502005010645D1 (de) Vorrichtung und Verfahren zur Erkennung von Behältern und Gebinden
DE502007001070D1 (de) Vorrichtung und verfahren zum verbinden von bändern
DE602006000487D1 (de) Verfahren und Vorrichtung zur Sprachdetektion
DE602006007776D1 (de) Verfahren und Vorrichtung zur Dehnungsmessung
DE602005002054D1 (de) Verfahren zum Nachweis von Testkörpern
DE502006009232D1 (de) Verfahren und Vorrichtung zum Entdecken von optischen Systemen in einem Geländebereich
DE602005013961D1 (de) Vorrichtung und verfahren zur verbindungsverifikation
DE602007008695D1 (de) Verfahren und vorrichtung zur erkennung und verhinderung von nebensprechen in einem multibandempfänger

Legal Events

Date Code Title Description
8364 No opposition during term of opposition