DE602005014737D1 - System und verfahren zur erkennung der breite eines datenbusses - Google Patents

System und verfahren zur erkennung der breite eines datenbusses

Info

Publication number
DE602005014737D1
DE602005014737D1 DE602005014737T DE602005014737T DE602005014737D1 DE 602005014737 D1 DE602005014737 D1 DE 602005014737D1 DE 602005014737 T DE602005014737 T DE 602005014737T DE 602005014737 T DE602005014737 T DE 602005014737T DE 602005014737 D1 DE602005014737 D1 DE 602005014737D1
Authority
DE
Germany
Prior art keywords
data bus
width
detecting
volatile memory
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005014737T
Other languages
English (en)
Inventor
Jerrold R Randell
Richard C Madter
Wei Yao Huang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BlackBerry Ltd
Original Assignee
Research in Motion Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Research in Motion Ltd filed Critical Research in Motion Ltd
Publication of DE602005014737D1 publication Critical patent/DE602005014737D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1678—Details of memory controller using bus width
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Traffic Control Systems (AREA)
DE602005014737T 2004-02-05 2005-02-03 System und verfahren zur erkennung der breite eines datenbusses Active DE602005014737D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54201204P 2004-02-05 2004-02-05
PCT/CA2005/000132 WO2005076143A1 (en) 2004-02-05 2005-02-03 System and method for detecting the width of a data bus

Publications (1)

Publication Number Publication Date
DE602005014737D1 true DE602005014737D1 (de) 2009-07-16

Family

ID=34837538

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005014737T Active DE602005014737D1 (de) 2004-02-05 2005-02-03 System und verfahren zur erkennung der breite eines datenbusses

Country Status (6)

Country Link
US (2) US7320045B2 (de)
EP (1) EP1711898B1 (de)
AT (1) ATE433158T1 (de)
CA (1) CA2554829C (de)
DE (1) DE602005014737D1 (de)
WO (1) WO2005076143A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2554829C (en) * 2004-02-05 2009-11-03 Research In Motion Limited System and method for detecting the width of a data bus
US8429326B2 (en) * 2005-09-12 2013-04-23 Mediatek Inc. Method and system for NAND-flash identification without reading device ID table
CZ302502B6 (cs) * 2005-09-26 2011-06-22 Microrisc S. R. O. Zarízení pro bezdrátovou komunikaci elektrických nebo elektronických zarízení nebo systému, zpusob jeho rízení a zpusob vytvorení generické platformy pro uživatelské aplikace v oblasti bezdrátové komunikace s tímto zarízením
US7321524B2 (en) 2005-10-17 2008-01-22 Rambus Inc. Memory controller with staggered request signal output
US8996784B2 (en) * 2006-03-09 2015-03-31 Mediatek Inc. Command controller, prefetch buffer and methods for accessing a serial flash in an embedded system
US7539967B1 (en) * 2006-05-05 2009-05-26 Altera Corporation Self-configuring components on a device
US7624211B2 (en) 2007-06-27 2009-11-24 Micron Technology, Inc. Method for bus width negotiation of data storage devices
US7542365B2 (en) 2007-09-27 2009-06-02 Freescale Semiconductor, Inc. Apparatus and method for accessing a synchronous serial memory having unknown address bit field size
TWI467579B (zh) * 2011-01-14 2015-01-01 Mstar Semiconductor Inc 電子裝置及其記憶體控制方法以及相關電腦可讀取儲存媒體
US9244867B1 (en) * 2011-06-01 2016-01-26 Altera Corporation Memory controller interface with adjustable port widths
JP5790532B2 (ja) * 2012-02-13 2015-10-07 セイコーエプソン株式会社 電子機器、及びメモリー制御方法
US9229888B1 (en) * 2012-07-30 2016-01-05 Altera Corporation Area-efficient dynamically-configurable memory controller
KR20170030304A (ko) 2015-09-09 2017-03-17 삼성전자주식회사 스위처블 감지 증폭기를 갖는 메모리 장치
KR20180021510A (ko) 2016-08-22 2018-03-05 삼성전자주식회사 메모리 장치 및 중앙 처리 장치
KR20180034738A (ko) 2016-09-26 2018-04-05 삼성전자주식회사 메모리 장치 및 그것의 분주 클록 보정 방법
KR20190105337A (ko) 2018-03-05 2019-09-17 삼성전자주식회사 반도체 메모리 장치
US11347581B2 (en) * 2020-04-27 2022-05-31 Western Digital Technologies, Inc. System for accelerated training of bit output timings

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61139866A (ja) * 1984-12-11 1986-06-27 Toshiba Corp マイクロプロセツサ
US5168562A (en) * 1989-02-21 1992-12-01 Compaq Computer Corporation Method and apparatus for determining the allowable data path width of a device in a computer system to avoid interference with other devices
US5255374A (en) * 1992-01-02 1993-10-19 International Business Machines Corporation Bus interface logic for computer system having dual bus architecture
JP2836321B2 (ja) * 1991-11-05 1998-12-14 三菱電機株式会社 データ処理装置
US5617546A (en) * 1993-12-22 1997-04-01 Acer Incorporated Data bus architecture compatible with 32-bit and 64-bit processors
JPH1078934A (ja) * 1996-07-01 1998-03-24 Sun Microsyst Inc パケット切替えコンピュータ・システムのマルチサイズ・バス結合システム
US6324666B1 (en) * 1998-04-20 2001-11-27 Mitsubishi Denki Kabushiki Kaisha Memory test device and method capable of achieving fast memory test without increasing chip pin number
US6263399B1 (en) * 1998-06-01 2001-07-17 Sun Microsystems, Inc. Microprocessor to NAND flash interface
DE60110227T2 (de) * 2000-06-27 2006-02-09 Koninklijke Philips Electronics N.V. Integrierte schaltung mit flash
US6449193B1 (en) * 2000-12-28 2002-09-10 Texas Instruments Incorporated Burst access memory system
KR100441608B1 (ko) * 2002-05-31 2004-07-23 삼성전자주식회사 낸드 플래시 메모리 인터페이스 장치
JP4257824B2 (ja) * 2002-07-03 2009-04-22 シャープ株式会社 半導体記憶装置
US20040128465A1 (en) * 2002-12-30 2004-07-01 Lee Micheil J. Configurable memory bus width
CA2554829C (en) * 2004-02-05 2009-11-03 Research In Motion Limited System and method for detecting the width of a data bus

Also Published As

Publication number Publication date
WO2005076143A1 (en) 2005-08-18
EP1711898A4 (de) 2007-02-07
US20050180206A1 (en) 2005-08-18
US7552267B2 (en) 2009-06-23
EP1711898A1 (de) 2006-10-18
CA2554829C (en) 2009-11-03
US7320045B2 (en) 2008-01-15
US20080028119A1 (en) 2008-01-31
CA2554829A1 (en) 2005-08-18
EP1711898B1 (de) 2009-06-03
ATE433158T1 (de) 2009-06-15

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