DE602005006745D1 - Verfahren zur vergrösserung einer routing-dichte für eine leiterplatte und eine solche leiterplatte - Google Patents

Verfahren zur vergrösserung einer routing-dichte für eine leiterplatte und eine solche leiterplatte

Info

Publication number
DE602005006745D1
DE602005006745D1 DE602005006745T DE602005006745T DE602005006745D1 DE 602005006745 D1 DE602005006745 D1 DE 602005006745D1 DE 602005006745 T DE602005006745 T DE 602005006745T DE 602005006745 T DE602005006745 T DE 602005006745T DE 602005006745 D1 DE602005006745 D1 DE 602005006745D1
Authority
DE
Germany
Prior art keywords
layer
pcb
electrical contacts
subset
magnifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602005006745T
Other languages
English (en)
Inventor
Lily Zhao
Michael Loo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Publication of DE602005006745D1 publication Critical patent/DE602005006745D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H05K1/114—Pad being close to via, but not surrounding the via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Sorting Of Articles (AREA)
  • Control Of Motors That Do Not Use Commutators (AREA)
DE602005006745T 2004-02-04 2005-02-03 Verfahren zur vergrösserung einer routing-dichte für eine leiterplatte und eine solche leiterplatte Active DE602005006745D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US54126104P 2004-02-04 2004-02-04
PCT/IB2005/050452 WO2005076677A1 (en) 2004-02-04 2005-02-03 Method for increasing a routing density for a circuit board and such a circuit board

Publications (1)

Publication Number Publication Date
DE602005006745D1 true DE602005006745D1 (de) 2008-06-26

Family

ID=34837472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602005006745T Active DE602005006745D1 (de) 2004-02-04 2005-02-03 Verfahren zur vergrösserung einer routing-dichte für eine leiterplatte und eine solche leiterplatte

Country Status (8)

Country Link
US (1) US20080251286A1 (de)
EP (1) EP1714530B1 (de)
JP (1) JP2007520888A (de)
CN (1) CN100525578C (de)
AT (1) ATE395806T1 (de)
DE (1) DE602005006745D1 (de)
TW (1) TW200531611A (de)
WO (1) WO2005076677A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100175911A1 (en) * 2009-01-15 2010-07-15 Ralph Morrison High-Speed Two-Layer and Multilayer Circuit Boards
TWI433614B (zh) 2011-08-23 2014-04-01 Mstar Semiconductor Inc 製作於印刷電路板上的球柵陣列
CN105704918B (zh) * 2016-02-01 2018-09-07 浪潮(北京)电子信息产业有限公司 一种高密度印制电路板
CN107734842A (zh) * 2017-09-22 2018-02-23 郑州云海信息技术有限公司 一种提升高密度孔印刷电路板信赖性的方法
US11640934B2 (en) * 2018-03-30 2023-05-02 Intel Corporation Lithographically defined vertical interconnect access (VIA) in dielectric pockets in a package substrate
US10784199B2 (en) * 2019-02-20 2020-09-22 Micron Technology, Inc. Component inter-digitated VIAS and leads
CN111739807B (zh) * 2020-08-06 2020-11-24 上海肇观电子科技有限公司 布线设计方法、布线结构以及倒装芯片

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5784262A (en) * 1995-11-06 1998-07-21 Symbios, Inc. Arrangement of pads and through-holes for semiconductor packages
US6232564B1 (en) * 1998-10-09 2001-05-15 International Business Machines Corporation Printed wiring board wireability enhancement
US6198635B1 (en) * 1999-05-18 2001-03-06 Vsli Technology, Inc. Interconnect layout pattern for integrated circuit packages and the like
US6150729A (en) * 1999-07-01 2000-11-21 Lsi Logic Corporation Routing density enhancement for semiconductor BGA packages and printed wiring boards
US6762366B1 (en) * 2001-04-27 2004-07-13 Lsi Logic Corporation Ball assignment for ball grid array package

Also Published As

Publication number Publication date
TW200531611A (en) 2005-09-16
EP1714530A1 (de) 2006-10-25
CN100525578C (zh) 2009-08-05
WO2005076677A1 (en) 2005-08-18
JP2007520888A (ja) 2007-07-26
ATE395806T1 (de) 2008-05-15
CN1914962A (zh) 2007-02-14
EP1714530B1 (de) 2008-05-14
US20080251286A1 (en) 2008-10-16

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Representative=s name: RICHTER, WERDERMANN, GERBAULET & HOFMANN, 20354 HA

8364 No opposition during term of opposition