TW200712799A - Stacked alignment mark and alignment method of photolithography process - Google Patents

Stacked alignment mark and alignment method of photolithography process

Info

Publication number
TW200712799A
TW200712799A TW094130644A TW94130644A TW200712799A TW 200712799 A TW200712799 A TW 200712799A TW 094130644 A TW094130644 A TW 094130644A TW 94130644 A TW94130644 A TW 94130644A TW 200712799 A TW200712799 A TW 200712799A
Authority
TW
Taiwan
Prior art keywords
alignment mark
stacked
alignment
photolithography process
layer
Prior art date
Application number
TW094130644A
Other languages
Chinese (zh)
Other versions
TWI299441B (en
Inventor
Wei-Sheng Chia
Chih-Jung Chen
Chung-An Chen
Chih-Chung Huang
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to TW94130644A priority Critical patent/TWI299441B/en
Publication of TW200712799A publication Critical patent/TW200712799A/en
Application granted granted Critical
Publication of TWI299441B publication Critical patent/TWI299441B/en

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  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Structure Of Printed Boards (AREA)
  • Liquid Crystal (AREA)

Abstract

A stacked alignment mark is described. The stacked alignment mark includes a first alignment mark and a second alignment mark. The first alignment mark which is constituted of a plurality of conductive lines is disposed in a first layer. The second alignment mark is disposed in a second layer, and the second layer is disposed under the first layer. The first alignment mark and the second alignment mark are formed on the corresponding region, and the second alignment mark at least includes the region of corresponding space of adjacent two conductive lines.
TW94130644A 2005-09-07 2005-09-07 Stacked alignment mark and alignment method of photolithography process TWI299441B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94130644A TWI299441B (en) 2005-09-07 2005-09-07 Stacked alignment mark and alignment method of photolithography process

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94130644A TWI299441B (en) 2005-09-07 2005-09-07 Stacked alignment mark and alignment method of photolithography process

Publications (2)

Publication Number Publication Date
TW200712799A true TW200712799A (en) 2007-04-01
TWI299441B TWI299441B (en) 2008-08-01

Family

ID=45069683

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94130644A TWI299441B (en) 2005-09-07 2005-09-07 Stacked alignment mark and alignment method of photolithography process

Country Status (1)

Country Link
TW (1) TWI299441B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI602035B (en) * 2014-04-11 2017-10-11 聯華電子股份有限公司 Overlap mark set and method for selecting recipe of measuring overlap error
TWI833216B (en) * 2022-03-03 2024-02-21 南亞科技股份有限公司 Semiconductor device with decoupling unit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI602035B (en) * 2014-04-11 2017-10-11 聯華電子股份有限公司 Overlap mark set and method for selecting recipe of measuring overlap error
TWI833216B (en) * 2022-03-03 2024-02-21 南亞科技股份有限公司 Semiconductor device with decoupling unit

Also Published As

Publication number Publication date
TWI299441B (en) 2008-08-01

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