DE60143584D1 - Abgleichkontrolle einer ätzmaske für ein transistorgate - Google Patents

Abgleichkontrolle einer ätzmaske für ein transistorgate

Info

Publication number
DE60143584D1
DE60143584D1 DE60143584T DE60143584T DE60143584D1 DE 60143584 D1 DE60143584 D1 DE 60143584D1 DE 60143584 T DE60143584 T DE 60143584T DE 60143584 T DE60143584 T DE 60143584T DE 60143584 D1 DE60143584 D1 DE 60143584D1
Authority
DE
Germany
Prior art keywords
transistorgate
compensation
paint mask
paint
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60143584T
Other languages
English (en)
Inventor
Massud Aminpur
David Wu
Scott Luning
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of DE60143584D1 publication Critical patent/DE60143584D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
DE60143584T 2000-10-17 2001-07-26 Abgleichkontrolle einer ätzmaske für ein transistorgate Expired - Lifetime DE60143584D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/690,152 US6482726B1 (en) 2000-10-17 2000-10-17 Control trimming of hard mask for sub-100 nanometer transistor gate
PCT/US2001/023577 WO2002033739A1 (en) 2000-10-17 2001-07-26 Control trimming of hard mask for transistor gate

Publications (1)

Publication Number Publication Date
DE60143584D1 true DE60143584D1 (de) 2011-01-13

Family

ID=24771302

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60143584T Expired - Lifetime DE60143584D1 (de) 2000-10-17 2001-07-26 Abgleichkontrolle einer ätzmaske für ein transistorgate

Country Status (8)

Country Link
US (1) US6482726B1 (de)
EP (1) EP1330838B1 (de)
JP (1) JP4936633B2 (de)
AU (1) AU2001279031A1 (de)
DE (1) DE60143584D1 (de)
GB (1) GB2387028B (de)
TW (1) TWI287832B (de)
WO (1) WO2002033739A1 (de)

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2810447B1 (fr) * 2000-06-16 2003-09-05 Commissariat Energie Atomique Procede de creation d'un etage de circuit integre ou conexistent des motifs fins et larges
JP3406302B2 (ja) * 2001-01-16 2003-05-12 株式会社半導体先端テクノロジーズ 微細パターンの形成方法、半導体装置の製造方法および半導体装置
US6864041B2 (en) * 2001-05-02 2005-03-08 International Business Machines Corporation Gate linewidth tailoring and critical dimension control for sub-100 nm devices using plasma etching
JP2003077900A (ja) * 2001-09-06 2003-03-14 Hitachi Ltd 半導体装置の製造方法
US6620715B1 (en) * 2002-03-29 2003-09-16 Cypress Semiconductor Corp. Method for forming sub-critical dimension structures in an integrated circuit
US6579809B1 (en) * 2002-05-16 2003-06-17 Advanced Micro Devices, Inc. In-situ gate etch process for fabrication of a narrow gate transistor structure with a high-k gate dielectric
US7268066B2 (en) 2002-07-31 2007-09-11 Advanced Micro Devices, Inc. Method for semiconductor gate line dimension reduction
US6849530B2 (en) * 2002-07-31 2005-02-01 Advanced Micro Devices Method for semiconductor gate line dimension reduction
US6617085B1 (en) * 2002-08-16 2003-09-09 International Business Machines Corporation Wet etch reduction of gate widths
JP2006501651A (ja) 2002-09-27 2006-01-12 東京エレクトロン株式会社 High−k誘電材料をエッチングするための方法及びシステム
US6706581B1 (en) * 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6794230B2 (en) * 2002-10-31 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Approach to improve line end shortening
US6720213B1 (en) * 2003-01-15 2004-04-13 International Business Machines Corporation Low-K gate spacers by fluorine implantation
US6780708B1 (en) 2003-03-05 2004-08-24 Advanced Micro Devices, Inc. Method of forming core and periphery gates including two critical masking steps to form a hard mask in a core region that includes a critical dimension less than achievable at a resolution limit of lithography
US6737325B1 (en) * 2003-03-06 2004-05-18 Texas Instruments Incorporated Method and system for forming a transistor having source and drain extensions
US6830996B2 (en) * 2003-03-24 2004-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Device performance improvement by heavily doped pre-gate and post polysilicon gate clean
KR100540475B1 (ko) * 2003-04-04 2006-01-10 주식회사 하이닉스반도체 미세 패턴 형성이 가능한 반도체 장치 제조 방법
US7186649B2 (en) * 2003-04-08 2007-03-06 Dongbu Electronics Co. Ltd. Submicron semiconductor device and a fabricating method thereof
US6933157B2 (en) * 2003-11-13 2005-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor wafer manufacturing methods employing cleaning delay period
US7354847B2 (en) * 2004-01-26 2008-04-08 Taiwan Semiconductor Manufacturing Company Method of trimming technology
US7172969B2 (en) * 2004-08-26 2007-02-06 Tokyo Electron Limited Method and system for etching a film stack
DE102004054558A1 (de) * 2004-11-11 2006-05-24 Infineon Technologies Ag Verfahren zur Herstellung einer resistiv schaltenden Speicherzelle, hergestellte Speicherzelle sowie daraus aufgebautes Speicherbauelement
JP2007081383A (ja) * 2005-08-15 2007-03-29 Fujitsu Ltd 微細構造の製造方法
KR100678638B1 (ko) * 2005-11-08 2007-02-05 삼성전자주식회사 반도체 소자의 제조 방법
JP2008060541A (ja) * 2006-08-29 2008-03-13 Korea Electronics Telecommun Gstカルコゲニドパターンを備える相変化メモリ素子の製造方法
TWI328221B (en) 2006-12-05 2010-08-01 Lite On It Corp Method of dynamically detecting write quality of recordable optical disc
US7897501B2 (en) * 2007-04-25 2011-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Method of fabricating a field-effect transistor having robust sidewall spacers
US8048764B2 (en) * 2009-09-30 2011-11-01 Taiwan Semiconductor Manufacturing Co., Ltd. Dual etch method of defining active area in semiconductor device
CN102110624B (zh) * 2009-12-23 2012-05-30 中芯国际集成电路制造(上海)有限公司 检测镍铂去除装置的方法
US8637411B2 (en) 2010-04-15 2014-01-28 Novellus Systems, Inc. Plasma activated conformal dielectric film deposition
US9892917B2 (en) * 2010-04-15 2018-02-13 Lam Research Corporation Plasma assisted atomic layer deposition of multi-layer films for patterning applications
US9257274B2 (en) 2010-04-15 2016-02-09 Lam Research Corporation Gapfill of variable aspect ratio features with a composite PEALD and PECVD method
US9997357B2 (en) 2010-04-15 2018-06-12 Lam Research Corporation Capped ALD films for doping fin-shaped channel regions of 3-D IC transistors
US9373500B2 (en) 2014-02-21 2016-06-21 Lam Research Corporation Plasma assisted atomic layer deposition titanium oxide for conformal encapsulation and gapfill applications
JP2014063776A (ja) * 2012-09-19 2014-04-10 Toshiba Corp 電界効果トランジスタ
JP6538300B2 (ja) 2012-11-08 2019-07-03 ノベラス・システムズ・インコーポレーテッドNovellus Systems Incorporated 感受性基材上にフィルムを蒸着するための方法
US9564312B2 (en) 2014-11-24 2017-02-07 Lam Research Corporation Selective inhibition in atomic layer deposition of silicon-containing films
US10566187B2 (en) 2015-03-20 2020-02-18 Lam Research Corporation Ultrathin atomic layer deposition film accuracy thickness control
US10204960B2 (en) 2015-09-17 2019-02-12 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming polysilicon gate structure in image sensor device
US10199223B2 (en) 2016-01-26 2019-02-05 Asm Ip Holding B.V. Semiconductor device fabrication using etch stop layer
US9773643B1 (en) 2016-06-30 2017-09-26 Lam Research Corporation Apparatus and method for deposition and etch in gap fill
US10062563B2 (en) 2016-07-01 2018-08-28 Lam Research Corporation Selective atomic layer deposition with post-dose treatment
US10037884B2 (en) 2016-08-31 2018-07-31 Lam Research Corporation Selective atomic layer deposition for gapfill using sacrificial underlayer
US10269559B2 (en) 2017-09-13 2019-04-23 Lam Research Corporation Dielectric gapfill of high aspect ratio features utilizing a sacrificial etch cap layer
US10840333B2 (en) * 2018-10-31 2020-11-17 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and method of manufacture
SG11202111962QA (en) 2019-05-01 2021-11-29 Lam Res Corp Modulated atomic layer deposition
US11342188B2 (en) * 2019-09-17 2022-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for doping high-k metal gates for tuning threshold voltages
WO2023056086A1 (en) * 2021-10-01 2023-04-06 PsiQuantum Corp. Patterning methods for photonic devices

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136402A (ja) * 1991-11-15 1993-06-01 Hitachi Ltd 半導体装置の製造方法
JP3371988B2 (ja) * 1993-08-31 2003-01-27 ソニー株式会社 薄膜の加工方法
US5431770A (en) 1993-10-13 1995-07-11 At&T Corp. Transistor gate formation
KR970004484B1 (ko) 1993-12-16 1997-03-28 금성일렉트론 주식회사 반도체 소자의 ldd mosfet 제조방법
US5976769A (en) * 1995-07-14 1999-11-02 Texas Instruments Incorporated Intermediate layer lithography
JPH09186166A (ja) * 1996-01-08 1997-07-15 Toshiba Corp 半導体装置の製造方法
JPH11297951A (ja) * 1998-02-13 1999-10-29 Hitachi Ltd 半導体集積回路装置およびその製造方法
US5989967A (en) 1998-04-30 1999-11-23 Advanced Micro Devices, Inc. Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
US6013570A (en) * 1998-07-17 2000-01-11 Advanced Micro Devices, Inc. LDD transistor using novel gate trim technique
US6136679A (en) * 1999-03-05 2000-10-24 Taiwan Semiconductor Manufacturing Company Gate micro-patterning process
US6103559A (en) * 1999-03-30 2000-08-15 Amd, Inc. (Advanced Micro Devices) Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
US6283131B1 (en) * 2000-09-25 2001-09-04 Taiwan Semiconductor Manufacturing Company In-situ strip process for polysilicon etching in deep sub-micron technology

Also Published As

Publication number Publication date
WO2002033739A1 (en) 2002-04-25
AU2001279031A1 (en) 2002-04-29
GB0311301D0 (en) 2003-06-25
JP2004512682A (ja) 2004-04-22
JP4936633B2 (ja) 2012-05-23
GB2387028A (en) 2003-10-01
EP1330838B1 (de) 2010-12-01
TWI287832B (en) 2007-10-01
US6482726B1 (en) 2002-11-19
EP1330838A1 (de) 2003-07-30
GB2387028B (en) 2004-11-10

Similar Documents

Publication Publication Date Title
DE60143584D1 (de) Abgleichkontrolle einer ätzmaske für ein transistorgate
DE60144323D1 (de) Geräte zur befestigung einer gewebefalte
ATE521185T1 (de) Abbildung eines indikators einer transportformatkombination für telekommunikation
DE50111949D1 (de) Komponente einer Strömungsmaschine
DE60114767D1 (de) Verfahren zur beschichtung einer oberfläche
ATE231715T1 (de) Zweikammerkartusche für vernebler
DE60022584D1 (de) Prothesenbausatz für ein Schultergelenk
DE69933399D1 (de) Dünnwandige Kartusche für wiederverwendbare Abgabevorrichtung
DE50103379D1 (de) Zerstäuberbrenner für ein fahrzeug-heizgerät
DE69925340D1 (de) Fernsteuerung für ein Anbaugerät eines Arbeitsfahrzeuges
DE69930832D1 (de) Benutzung einer zusammensetzung für eine antireflexunterschicht
DE69823201T2 (de) Schnittstelle für ein hochintegriertes ethernet netzwerk
DE60204390D1 (de) Form für Herstellung einer elastischen Raupenkette
DE60123163D1 (de) Auftragen einer klaren Deckflüssigkeit
DE60210718D1 (de) Verfahren zur Herstellung einer Reparaturlackierung
DE69920729D1 (de) Farbauswahl und identifikation für baukünstlerische beschichtungen
NO20011556D0 (no) Grohemmende maling
DE60044283D1 (de) Harzzusammensetzung für wässerigen Lack
DE60103344D1 (de) Verfahren zur Herstellung einer Prothese
DE69914409D1 (de) Verfahren zur Vorbehandlung einer Oberfläche für keramische Beschichtungen
DE69916232D1 (de) Zusammensetzung zur Herstellung einer Metall-Keramik-Beschichtung
DE60220204D1 (de) System einer Patrone für Heftklammern
ATE274005T1 (de) BINDEMITTEL FÜR ßSOFT-FEELß-LACKE
DE60102843D1 (de) Montageanordnung für den Dreieckslenker einer Aufhängung
NO20005408L (no) Fremgangsmate for a redusere tendens til beleggdannelse for brukt olje