DE60136974D1 - Nachschlagtabelle für ein Nutzerprogrammierbares Gatterfeld mit einem schnellen Lesedekodierer - Google Patents

Nachschlagtabelle für ein Nutzerprogrammierbares Gatterfeld mit einem schnellen Lesedekodierer

Info

Publication number
DE60136974D1
DE60136974D1 DE60136974T DE60136974T DE60136974D1 DE 60136974 D1 DE60136974 D1 DE 60136974D1 DE 60136974 T DE60136974 T DE 60136974T DE 60136974 T DE60136974 T DE 60136974T DE 60136974 D1 DE60136974 D1 DE 60136974D1
Authority
DE
Germany
Prior art keywords
programmable gate
gate array
lookup table
user programmable
fast read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60136974T
Other languages
English (en)
Inventor
Richard A Carberry
Steven P Young
Trevor J Bauer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60136974D1 publication Critical patent/DE60136974D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
DE60136974T 2000-05-05 2001-04-06 Nachschlagtabelle für ein Nutzerprogrammierbares Gatterfeld mit einem schnellen Lesedekodierer Expired - Lifetime DE60136974D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/566,052 US6529040B1 (en) 2000-05-05 2000-05-05 FPGA lookup table with speed read decoder

Publications (1)

Publication Number Publication Date
DE60136974D1 true DE60136974D1 (de) 2009-01-22

Family

ID=24261267

Family Applications (2)

Application Number Title Priority Date Filing Date
DE60136974T Expired - Lifetime DE60136974D1 (de) 2000-05-05 2001-04-06 Nachschlagtabelle für ein Nutzerprogrammierbares Gatterfeld mit einem schnellen Lesedekodierer
DE60131078T Expired - Lifetime DE60131078T2 (de) 2000-05-05 2001-04-06 Nachschlagtabelle für ein nutzerprogrammierbares gatterfeld mit einem schnellen lesedekodierer

Family Applications After (1)

Application Number Title Priority Date Filing Date
DE60131078T Expired - Lifetime DE60131078T2 (de) 2000-05-05 2001-04-06 Nachschlagtabelle für ein nutzerprogrammierbares gatterfeld mit einem schnellen lesedekodierer

Country Status (5)

Country Link
US (2) US6529040B1 (de)
EP (2) EP1489745B1 (de)
CA (2) CA2411650C (de)
DE (2) DE60136974D1 (de)
WO (1) WO2001086812A2 (de)

Families Citing this family (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ITRM20010298A1 (it) * 2001-05-31 2002-12-02 Micron Technology Inc Interfaccia di comando di utilizzatore con decodificatore programmabile.
US6677779B1 (en) * 2001-03-29 2004-01-13 Atheros Communications, Inc. Flexible control interface for integrated circuit
US20030068038A1 (en) * 2001-09-28 2003-04-10 Bedros Hanounik Method and apparatus for encrypting data
US6781409B2 (en) * 2001-10-10 2004-08-24 Altera Corporation Apparatus and methods for silicon-on-insulator transistors in programmable logic devices
WO2003079549A1 (en) * 2002-03-18 2003-09-25 Koninklijke Philips Electronics N.V. Configuration memory implementation for lut-based reconfigurable logic architectures
US6992503B2 (en) 2002-07-08 2006-01-31 Viciciv Technology Programmable devices with convertibility to customizable devices
US7112994B2 (en) 2002-07-08 2006-09-26 Viciciv Technology Three dimensional integrated circuits
US8643162B2 (en) 2007-11-19 2014-02-04 Raminda Udaya Madurawe Pads and pin-outs in three dimensional integrated circuits
US6966044B2 (en) * 2002-12-09 2005-11-15 Lsi Logic Corporation Method for composing memory on programmable platform devices to meet varied memory requirements with a fixed set of resources
US7386826B1 (en) 2003-06-24 2008-06-10 Xilinx, Inc. Using redundant routing to reduce susceptibility to single event upsets in PLD designs
US20050093577A1 (en) * 2003-11-04 2005-05-05 Liem Nguyen Multiplexer circuits
US6914450B2 (en) * 2003-11-06 2005-07-05 International Business Machines Corporation Register-file bit-read method and apparatus
DE10354501B4 (de) * 2003-11-21 2007-07-05 Infineon Technologies Ag Logik-Schaltkreis-Anordnung
US7386812B2 (en) * 2003-11-21 2008-06-10 Infineon Technologies Ag Logic basic cell and logic basic cell arrangement
US7167021B1 (en) 2003-11-24 2007-01-23 Altera Corporation Logic device logic modules having improved arithmetic circuitry
US7019557B2 (en) * 2003-12-24 2006-03-28 Viciciv Technology Look-up table based logic macro-cells
US7030651B2 (en) 2003-12-04 2006-04-18 Viciciv Technology Programmable structured arrays
DE10357209A1 (de) * 2003-12-08 2005-07-07 Infineon Technologies Ag Logik-Grundzelle, Logik-Grundzellen-Anordnung und Logik-Vorrichtung
US7279936B2 (en) * 2003-12-08 2007-10-09 Infineon Technologies Ag Logic basic cell, logic basic cell arrangement and logic device
US7030658B2 (en) * 2004-01-23 2006-04-18 Kabushiki Kaisha Toshiba Systems and methods for operating logic circuits
US6956399B1 (en) * 2004-02-05 2005-10-18 Xilinx, Inc. High-speed lookup table circuits and methods for programmable logic devices
DE102004006769B3 (de) * 2004-02-11 2005-08-11 Infineon Technologies Ag Auslesevorrichtung
US7284222B1 (en) 2004-06-30 2007-10-16 Tabula, Inc. Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit
US7193440B1 (en) * 2004-02-14 2007-03-20 Herman Schmit Configurable circuits, IC's, and systems
US7622951B2 (en) * 2004-02-14 2009-11-24 Tabula, Inc. Via programmable gate array with offset direct connections
US7425841B2 (en) 2004-02-14 2008-09-16 Tabula Inc. Configurable circuits, IC's, and systems
US7126381B1 (en) 2004-02-14 2006-10-24 Herman Schmit VPA interconnect circuit
US7109752B1 (en) 2004-02-14 2006-09-19 Herman Schmit Configurable circuits, IC's, and systems
US7126373B1 (en) * 2004-02-14 2006-10-24 Herman Schmit Configurable logic circuits with commutative properties
US7157933B1 (en) 2004-02-14 2007-01-02 Herman Schmit Configurable circuits, IC's, and systems
US7167025B1 (en) 2004-02-14 2007-01-23 Herman Schmit Non-sequentially configurable IC
US7193432B1 (en) 2004-02-14 2007-03-20 Herman Schmit VPA logic circuits
US6992505B1 (en) * 2004-03-09 2006-01-31 Xilinx, Inc. Structures and methods of implementing a pass gate multiplexer with pseudo-differential input signals
DE102004011433A1 (de) * 2004-03-09 2005-10-20 Infineon Technologies Ag Logik-Grundzelle, Logik-Grundzellen-Anordnung und Logik-Vorrichtung
DE102004025581B4 (de) * 2004-05-25 2008-02-14 Infineon Technologies Ag Logik-Grundzelle und Logik-Grundzellen-Anordnung
US7439766B2 (en) * 2004-06-30 2008-10-21 Tabula, Inc. Configurable logic circuits with commutative properties
US7282950B1 (en) * 2004-11-08 2007-10-16 Tabula, Inc. Configurable IC's with logic resources with offset connections
US7312630B2 (en) 2004-06-30 2007-12-25 Tabula, Inc. Configurable integrated circuit with built-in turns
US7408382B2 (en) * 2004-06-30 2008-08-05 Tabula, Inc. Configurable circuits, IC's, and systems
US7193438B1 (en) 2004-06-30 2007-03-20 Andre Rohe Configurable integrated circuit with offset connection
US7449915B2 (en) * 2004-06-30 2008-11-11 Tabula Inc. VPA logic circuits
US7145361B1 (en) * 2004-06-30 2006-12-05 Andre Rohe Configurable integrated circuit with different connection schemes
US7573296B2 (en) 2004-11-08 2009-08-11 Tabula Inc. Configurable IC with configurable routing resources that have asymmetric input and/or outputs
US7342415B2 (en) * 2004-11-08 2008-03-11 Tabula, Inc. Configurable IC with interconnect circuits that also perform storage operations
US7301368B2 (en) * 2005-03-15 2007-11-27 Tabula, Inc. Embedding memory within tile arrangement of a configurable IC
US7917559B2 (en) * 2004-11-08 2011-03-29 Tabula, Inc. Configurable IC's with configurable logic circuits that perform adder and/or subtractor operations
US7268586B1 (en) 2004-11-08 2007-09-11 Tabula, Inc. Method and apparatus for accessing stored data in a reconfigurable IC
US7330050B2 (en) * 2004-11-08 2008-02-12 Tabula, Inc. Storage elements for a configurable IC and method and apparatus for accessing data stored in the storage elements
US7317331B2 (en) 2004-11-08 2008-01-08 Tabula, Inc. Reconfigurable IC that has sections running at different reconfiguration rates
US7276933B1 (en) 2004-11-08 2007-10-02 Tabula, Inc. Reconfigurable IC that has sections running at different looperness
US7295037B2 (en) * 2004-11-08 2007-11-13 Tabula, Inc. Configurable IC with routing circuits with offset connections
US7224181B1 (en) * 2004-11-08 2007-05-29 Herman Schmit Clock distribution in a configurable IC
US7743085B2 (en) * 2004-11-08 2010-06-22 Tabula, Inc. Configurable IC with large carry chains
US7242216B1 (en) 2004-11-08 2007-07-10 Herman Schmit Embedding memory between tile arrangement of a configurable IC
US7259587B1 (en) * 2004-11-08 2007-08-21 Tabula, Inc. Configurable IC's with configurable logic resources that have asymetric inputs and/or outputs
US20070244958A1 (en) * 2004-11-08 2007-10-18 Jason Redgrave Configurable IC's with carry bypass circuitry
US7236009B1 (en) * 2004-12-01 2007-06-26 Andre Rohe Operational time extension
US7496879B2 (en) * 2004-12-01 2009-02-24 Tabula, Inc. Concurrent optimization of physical design and operational cycle assignment
US7428721B2 (en) * 2004-12-01 2008-09-23 Tabula, Inc. Operational cycle assignment in a configurable IC
US7358761B1 (en) * 2005-01-21 2008-04-15 Csitch Corporation Versatile multiplexer-structures in programmable logic using serial chaining and novel selection schemes
US7825684B2 (en) * 2005-03-15 2010-11-02 Tabula, Inc. Variable width management for a memory of a configurable IC
US7530033B2 (en) * 2005-03-15 2009-05-05 Tabula, Inc. Method and apparatus for decomposing functions in a configurable IC
US7298169B2 (en) * 2005-03-15 2007-11-20 Tabula, Inc Hybrid logic/interconnect circuit in a configurable IC
US7310003B2 (en) * 2005-03-15 2007-12-18 Tabula, Inc. Configurable IC with interconnect circuits that have select lines driven by user signals
US7224182B1 (en) * 2005-03-15 2007-05-29 Brad Hutchings Hybrid configurable circuit for a configurable IC
US7230869B1 (en) 2005-03-15 2007-06-12 Jason Redgrave Method and apparatus for accessing contents of memory cells
MX2007013075A (es) * 2005-04-21 2008-01-11 Nutricia Nv Suplemento nutritivo para pacientes con vih.
US7256612B1 (en) 2005-06-14 2007-08-14 Xilinx, Inc. Programmable logic block providing carry chain with programmable initialization values
US7215138B1 (en) * 2005-06-14 2007-05-08 Xilinx, Inc. Programmable lookup table with dual input and output terminals in shift register mode
US7274214B1 (en) 2005-06-14 2007-09-25 Xilinx, Inc. Efficient tile layout for a programmable logic device
US7375552B1 (en) 2005-06-14 2008-05-20 Xilinx, Inc. Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure
US7265576B1 (en) 2005-06-14 2007-09-04 Xilinx, Inc. Programmable lookup table with dual input and output terminals in RAM mode
US7268587B1 (en) 2005-06-14 2007-09-11 Xilinx, Inc. Programmable logic block with carry chains providing lookahead functions of different lengths
US7253658B1 (en) 2005-06-14 2007-08-07 Xilinx, Inc. Integrated circuit providing direct access to multi-directional interconnect lines in a general interconnect structure
US7276934B1 (en) 2005-06-14 2007-10-02 Xilinx, Inc. Integrated circuit with programmable routing structure including diagonal interconnect lines
US7804719B1 (en) 2005-06-14 2010-09-28 Xilinx, Inc. Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode
US7126858B1 (en) * 2005-06-17 2006-10-24 Altera Corporation Apparatus for emulating asynchronous clear in memory structure and method for implementing the same
US7788478B2 (en) * 2005-07-15 2010-08-31 Tabula, Inc. Accessing multiple user states concurrently in a configurable IC
US8463836B1 (en) 2005-11-07 2013-06-11 Tabula, Inc. Performing mathematical and logical operations in multiple sub-cycles
US7765249B1 (en) 2005-11-07 2010-07-27 Tabula, Inc. Use of hybrid interconnect/logic circuits for multiplication
US7818361B1 (en) 2005-11-07 2010-10-19 Tabula, Inc. Method and apparatus for performing two's complement multiplication
US7372297B1 (en) 2005-11-07 2008-05-13 Tabula Inc. Hybrid interconnect/logic circuits enabling efficient replication of a function in several sub-cycles to save logic and routing resources
US7262633B1 (en) * 2005-11-11 2007-08-28 Tabula, Inc. Via programmable gate array with offset bit lines
US7461362B1 (en) 2005-12-01 2008-12-02 Tabula, Inc. Replacing circuit design elements with their equivalents
US7679401B1 (en) * 2005-12-01 2010-03-16 Tabula, Inc. User registers implemented with routing circuits in a configurable IC
US7489162B1 (en) 2005-12-01 2009-02-10 Tabula, Inc. Users registers in a reconfigurable IC
US7504858B1 (en) 2006-03-08 2009-03-17 Tabula, Inc. Configurable integrated circuit with parallel non-neighboring offset connections
US7797497B1 (en) * 2006-03-08 2010-09-14 Tabula, Inc. System and method for providing more logical memory ports than physical memory ports
US7694083B1 (en) * 2006-03-08 2010-04-06 Tabula, Inc. System and method for providing a virtual memory architecture narrower and deeper than a physical memory architecture
US7518400B1 (en) 2006-03-08 2009-04-14 Tabula, Inc. Barrel shifter implemented on a configurable integrated circuit
US7486111B2 (en) * 2006-03-08 2009-02-03 Tier Logic, Inc. Programmable logic devices comprising time multiplexed programmable interconnect
US7609085B1 (en) 2006-03-08 2009-10-27 Tabula, Inc. Configurable integrated circuit with a 4-to-1 multiplexer
US7529992B1 (en) 2006-03-27 2009-05-05 Tabula, Inc. Configurable integrated circuit with error correcting circuitry
US7669097B1 (en) 2006-03-27 2010-02-23 Tabula, Inc. Configurable IC with error detection and correction circuitry
US7812633B1 (en) * 2006-04-03 2010-10-12 Altera Corporation Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device
CN100442783C (zh) * 2006-04-12 2008-12-10 杭州华三通信技术有限公司 基于现场可编程逻辑阵列的读写缓存单元的方法及装置
US7397276B1 (en) * 2006-06-02 2008-07-08 Lattice Semiconductor Corporation Logic block control architectures for programmable logic devices
US7378872B1 (en) * 2006-06-02 2008-05-27 Lattice Semiconductor Corporation Programmable logic device architecture with multiple slice types
US7587697B1 (en) 2006-12-12 2009-09-08 Tabula, Inc. System and method of mapping memory blocks in a configurable integrated circuit
US7930666B1 (en) 2006-12-12 2011-04-19 Tabula, Inc. System and method of providing a memory hierarchy
EP2597776A3 (de) * 2007-03-20 2014-08-20 Tabula, Inc. Konfigurierbares IC mit einem koppelfeld mit speicherelementen
US7535252B1 (en) 2007-03-22 2009-05-19 Tabula, Inc. Configurable ICs that conditionally transition through configuration data sets
US7928761B2 (en) 2007-09-06 2011-04-19 Tabula, Inc. Configuration context switcher with a latch
US7940082B1 (en) * 2007-12-28 2011-05-10 Altera Corporation Circuits and method for bypassing a static configuration in a programmable logic device to implement a dynamic multiplexer
US8863067B1 (en) 2008-02-06 2014-10-14 Tabula, Inc. Sequential delay analysis by placement engines
US8166435B2 (en) 2008-06-26 2012-04-24 Tabula, Inc. Timing operations in an IC with configurable circuits
US8230375B2 (en) 2008-09-14 2012-07-24 Raminda Udaya Madurawe Automated metal pattern generation for integrated circuits
US7786749B1 (en) * 2009-05-19 2010-08-31 Sillcon Storage Technology, Inc. Programmable integrated circuit having built in test circuit
WO2011123151A1 (en) 2010-04-02 2011-10-06 Tabula Inc. System and method for reducing reconfiguration power usage
US8760193B2 (en) 2011-07-01 2014-06-24 Tabula, Inc. Configurable storage elements
US9148151B2 (en) 2011-07-13 2015-09-29 Altera Corporation Configurable storage elements
US9203397B1 (en) 2011-12-16 2015-12-01 Altera Corporation Delaying start of user design execution
US20150154005A1 (en) * 2013-12-02 2015-06-04 Kuo-Tseng Tseng Methods and Apparatuses for Performing Multiplication
US9509307B1 (en) * 2014-09-22 2016-11-29 Xilinx, Inc. Interconnect multiplexers and methods of reducing contention currents in an interconnect multiplexer
US9710199B2 (en) 2014-11-07 2017-07-18 International Business Machines Corporation Non-volatile memory data storage with low read amplification
US10162700B2 (en) 2014-12-23 2018-12-25 International Business Machines Corporation Workload-adaptive data packing algorithm
US10027326B2 (en) * 2015-01-21 2018-07-17 Nec Corporation Reconfigurable circuit
US9712190B2 (en) 2015-09-24 2017-07-18 International Business Machines Corporation Data packing for compression-enabled storage systems
US9870285B2 (en) 2015-11-18 2018-01-16 International Business Machines Corporation Selectively de-straddling data pages in non-volatile memory
CN111142840B (zh) * 2019-12-27 2023-06-09 深圳鲲云信息科技有限公司 基于fpga的数据计算方法和装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750155A (en) 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US5212652A (en) * 1989-08-15 1993-05-18 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure
US5414377A (en) * 1992-12-21 1995-05-09 Xilinx, Inc. Logic block with look-up table for configuration and memory
US5315178A (en) * 1993-08-27 1994-05-24 Hewlett-Packard Company IC which can be used as a programmable logic cell array or as a register file
FR2729528A1 (fr) * 1995-01-13 1996-07-19 Suisse Electronique Microtech Circuit de multiplexage
JPH0983348A (ja) * 1995-09-14 1997-03-28 Hitachi Ltd 可変論理回路
KR0173955B1 (ko) * 1996-02-01 1999-04-01 김광호 에너지 절약형 패스 트랜지스터 로직회로 및 이를 이용한 전가산기
US5889413A (en) 1996-11-22 1999-03-30 Xilinx, Inc. Lookup tables which double as shift registers
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US5933369A (en) 1997-02-28 1999-08-03 Xilinx, Inc. RAM with synchronous write port using dynamic latches
US5764564A (en) 1997-03-11 1998-06-09 Xilinx, Inc. Write-assisted memory cell and method of operating same
JP3701781B2 (ja) * 1997-11-28 2005-10-05 株式会社ルネサステクノロジ 論理回路とその作成方法

Also Published As

Publication number Publication date
EP1489745B1 (de) 2008-12-10
US6529040B1 (en) 2003-03-04
EP1287615B1 (de) 2007-10-24
CA2676132C (en) 2012-01-03
DE60131078T2 (de) 2008-08-07
CA2411650A1 (en) 2001-11-15
US20030071653A1 (en) 2003-04-17
EP1287615A2 (de) 2003-03-05
WO2001086812A3 (en) 2002-06-27
DE60131078D1 (de) 2007-12-06
US6621296B2 (en) 2003-09-16
CA2676132A1 (en) 2001-11-15
EP1489745A3 (de) 2006-06-28
CA2411650C (en) 2012-11-27
WO2001086812A2 (en) 2001-11-15
EP1489745A2 (de) 2004-12-22

Similar Documents

Publication Publication Date Title
DE60136974D1 (de) Nachschlagtabelle für ein Nutzerprogrammierbares Gatterfeld mit einem schnellen Lesedekodierer
EP1440446A4 (de) Nichtflüchtiger speicher mit temperaturkompensierter datenleseoperation
ATA7652003A (de) Möbel mit einem bewegbaren möbelteil
DE602004010303D1 (de) Mehrere schnittstellen in einem speichergehäuse
GB0525079D0 (en) Non-volatile memory disc
DE60128960D1 (de) Architektur für ziegelförmig aufbaubares nutzerprogrammierbares gatterfeld
ATE455076T1 (de) Mehrfach unterteilter behälter mit zapfhahn
DE60212979D1 (de) Kosmetikbehälter mit einem magnetischen scharnier
DE60328950D1 (de) Blattkassette mit einem Anschlagelement
DE60128679D1 (de) Nachschlagtabelle für nutzerprogrammierbares gatterfeld mit zwei toren für schreiblese- und schieberegister- modus
ATE302762T1 (de) Oxazolidinon-thioamide mit piperazinamid- substituenten
DE602004022489D1 (de) in einem Zeitsprung Ultra-Breitband Signal
SG113487A1 (en) Multiple-bit storage element for binary optical display element
DE50107589D1 (de) Schrittschaltwerk mit einem Klemmgesperre
DE60326103D1 (de) Container mit bewegbarer Trennwand
DE50213243D1 (de) Eitung mit einem vorgespannten anschlussst ck
DE69919992D1 (de) Verteilter Speicher mit programmierbarer Grösse
DE60041037D1 (de) Strang-programmierbarer nichtflüchtiger Speicher mit NOR-Architektur
DE60313639D1 (de) Scheibenwischer mit einem mobilen doppelwischer
DE60308877D1 (de) Biologisch abbaubare filterzigarette mit zwei dichten
DE10196011T1 (de) Flash mit konsistenter Latenz für Leseoperationen
DE602004020144D1 (de) Moduläre Datenspeicherbibliothek mit automatischer Konfiguration
AU2003226879A1 (en) Memory cell with non-destructive one-time programming
DE69939835D1 (de) Addierschaltung mit scheinfehlern
DE60030061D1 (de) Ein lesekanal mit programmierbarer bandbreitensteuerung

Legal Events

Date Code Title Description
8364 No opposition during term of opposition