DE10196011T1 - Flash mit konsistenter Latenz für Leseoperationen - Google Patents

Flash mit konsistenter Latenz für Leseoperationen

Info

Publication number
DE10196011T1
DE10196011T1 DE10196011T DE10196011T DE10196011T1 DE 10196011 T1 DE10196011 T1 DE 10196011T1 DE 10196011 T DE10196011 T DE 10196011T DE 10196011 T DE10196011 T DE 10196011T DE 10196011 T1 DE10196011 T1 DE 10196011T1
Authority
DE
Germany
Prior art keywords
flash
read operations
consistent latency
latency
consistent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE10196011T
Other languages
English (en)
Other versions
DE10196011B3 (de
Inventor
Frankie F Roohparvar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/567,733 external-priority patent/US6615307B1/en
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE10196011T1 publication Critical patent/DE10196011T1/de
Application granted granted Critical
Publication of DE10196011B3 publication Critical patent/DE10196011B3/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1694—Configuration of memory controller to different memory types
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045—Read-write mode select circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/105—Aspects related to pads, pins or terminals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2281—Timing of a read operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/229—Timing of a write operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22—Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)
DE10196011T 2000-03-30 2001-03-30 Synchrone Speichereinrichtung und Verfahren zum Lesen von Daten von einer synchronen Speichereinrichtung Expired - Fee Related DE10196011B3 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US19350600P 2000-03-30 2000-03-30
US60/193,506 2000-03-30
US09/567,733 2000-05-10
US09/567,733 US6615307B1 (en) 2000-05-10 2000-05-10 Flash with consistent latency for read operations
PCT/US2001/010040 WO2001075896A2 (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations

Publications (2)

Publication Number Publication Date
DE10196011T1 true DE10196011T1 (de) 2003-03-13
DE10196011B3 DE10196011B3 (de) 2012-07-26

Family

ID=26889061

Family Applications (1)

Application Number Title Priority Date Filing Date
DE10196011T Expired - Fee Related DE10196011B3 (de) 2000-03-30 2001-03-30 Synchrone Speichereinrichtung und Verfahren zum Lesen von Daten von einer synchronen Speichereinrichtung

Country Status (5)

Country Link
JP (1) JP3631209B2 (de)
KR (1) KR100508042B1 (de)
AU (1) AU2001289291A1 (de)
DE (1) DE10196011B3 (de)
WO (1) WO2001075896A2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615307B1 (en) * 2000-05-10 2003-09-02 Micron Technology, Inc. Flash with consistent latency for read operations
KR100618696B1 (ko) * 2004-04-28 2006-09-08 주식회사 하이닉스반도체 인식 정보를 갖는 메모리 장치
KR100762259B1 (ko) * 2005-09-12 2007-10-01 삼성전자주식회사 버스트 읽기 레이턴시 기능을 갖는 낸드 플래시 메모리장치
JP5266589B2 (ja) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 不揮発性半導体記憶装置
US20150095551A1 (en) * 2013-09-30 2015-04-02 Micron Technology, Inc. Volatile memory architecutre in non-volatile memory devices and related controllers
US11048649B2 (en) 2018-10-17 2021-06-29 Macronix International Co., Ltd. Non-sequential page continuous read
US10977121B2 (en) 2018-10-17 2021-04-13 Macronix International Co., Ltd. Fast page continuous read
TWI727449B (zh) * 2018-10-17 2021-05-11 旺宏電子股份有限公司 非循序頁面連續讀取
US10957384B1 (en) 2019-09-24 2021-03-23 Macronix International Co., Ltd. Page buffer structure and fast continuous read
US11302366B2 (en) 2020-03-06 2022-04-12 Macronix International Co., Ltd. Method and system for enhanced read performance in low pin count interface
US11249913B2 (en) 2020-03-06 2022-02-15 Macronix International Co., Ltd. Continuous read with multiple read commands

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5713005A (en) * 1995-02-10 1998-01-27 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
US5889726A (en) * 1997-11-17 1999-03-30 Micron Electronics, Inc. Apparatus for providing additional latency for synchronously accessed memory
US5978311A (en) * 1998-03-03 1999-11-02 Micron Technology, Inc. Memory with combined synchronous burst and bus efficient functionality
KR100306966B1 (ko) * 1998-08-04 2001-11-30 윤종용 동기형버스트반도체메모리장치

Also Published As

Publication number Publication date
WO2001075896A2 (en) 2001-10-11
WO2001075896A3 (en) 2002-02-28
JP2003529883A (ja) 2003-10-07
WO2001075896A9 (en) 2002-12-19
KR100508042B1 (ko) 2005-08-17
JP3631209B2 (ja) 2005-03-23
DE10196011B3 (de) 2012-07-26
KR20030014380A (ko) 2003-02-17
AU2001289291A1 (en) 2001-10-15

Similar Documents

Publication Publication Date Title
DE10196380T1 (de) Nicht-flüchtiger Cache
NO20025115L (no) Muskarin agonister
DE60325509D1 (de) Schaltung für präzise speicherleseoperationen
PT1341791E (pt) Imidazoquinolinas substituidas com tioeter
DE60130381D1 (de) Mutterführung
DE50100071D1 (de) Drehsteller
DE10196179T1 (de) Verbesserte Abgleichtechnik für Speichervorrichtungen
DE50111881D1 (de) MRAM-Speicher
DE50103020D1 (de) Positioniereinheit
DE50108537D1 (de) Haltevorrichtung
NO20025508L (no) Substituerte tioacetamider
DE60136416D1 (de) Kraftverstärkender Mechanismus für Hefter
DE60136801D1 (de) Schreibgerät
DE50000262D1 (de) Schreib-/lesearchitektur für mram
DE60140039D1 (de) Löschverfahren für einen Flash-Speicher
DE10196011T1 (de) Flash mit konsistenter Latenz für Leseoperationen
DE60100508D1 (de) Prufer mit auswechselbarem flashspeicher
DE60138857D1 (de) Multiport-Cachespeicher
DE50007505D1 (de) Positioniervorrichtung
DE60136482D1 (de) Wortleitungsdekodierungsarchitektur für flashspeicher
DK1339416T3 (da) Sporelementer
DE60319784D1 (de) Lesevorrichtung
DE50114117D1 (de) Multiprozessor-Anordnung
DE60144004D1 (de) Kugelschreiber
DE60100450D1 (de) Multiprozessorschnittstelle

Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law

Ref document number: 10196011

Country of ref document: DE

Date of ref document: 20030313

Kind code of ref document: P

8125 Change of the main classification

Ipc: G11C 1626

R016 Response to examination communication
R018 Grant decision by examination section/examining division
R020 Patent grant now final

Effective date: 20121027

R081 Change of applicant/patentee

Owner name: ROUND ROCK RESEARCH, LLC (N.D.GES.D. STAATES D, US

Free format text: FORMER OWNER: MICRON TECHNOLOGY, INC., BOISE, ID., US

R082 Change of representative

Representative=s name: PATENTANWAELTE STAEGER & SPERLING PARTNERSCHAF, DE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee