WO2001075896A3 - Flash with consistent latency for read operations - Google Patents

Flash with consistent latency for read operations Download PDF

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Publication number
WO2001075896A3
WO2001075896A3 PCT/US2001/010040 US0110040W WO0175896A3 WO 2001075896 A3 WO2001075896 A3 WO 2001075896A3 US 0110040 W US0110040 W US 0110040W WO 0175896 A3 WO0175896 A3 WO 0175896A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
data
flash
read operations
consistent latency
Prior art date
Application number
PCT/US2001/010040
Other languages
French (fr)
Other versions
WO2001075896A2 (en
WO2001075896A9 (en
Inventor
Frankie F Roohparvar
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US19350600P priority Critical
Priority to US60/193,506 priority
Priority to US09/567,733 priority patent/US6615307B1/en
Priority to US09/567,733 priority
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of WO2001075896A2 publication Critical patent/WO2001075896A2/en
Publication of WO2001075896A3 publication Critical patent/WO2001075896A3/en
Publication of WO2001075896A9 publication Critical patent/WO2001075896A9/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.
PCT/US2001/010040 2000-03-30 2001-03-30 Flash with consistent latency for read operations WO2001075896A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US19350600P true 2000-03-30 2000-03-30
US60/193,506 2000-03-30
US09/567,733 US6615307B1 (en) 2000-05-10 2000-05-10 Flash with consistent latency for read operations
US09/567,733 2000-05-10

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
KR20027013097A KR100508042B1 (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations
DE10196011T DE10196011B3 (en) 2000-03-30 2001-03-30 Synchronous memory device and method for reading data from a synchronous memory device
AU8929101A AU8929101A (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations
JP2001573488A JP3631209B2 (en) 2000-03-30 2001-03-30 Flash with consistent latency in read processing

Publications (3)

Publication Number Publication Date
WO2001075896A2 WO2001075896A2 (en) 2001-10-11
WO2001075896A3 true WO2001075896A3 (en) 2002-02-28
WO2001075896A9 WO2001075896A9 (en) 2002-12-19

Family

ID=26889061

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010040 WO2001075896A2 (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations

Country Status (5)

Country Link
JP (1) JP3631209B2 (en)
KR (1) KR100508042B1 (en)
AU (1) AU8929101A (en)
DE (1) DE10196011B3 (en)
WO (1) WO2001075896A2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615307B1 (en) * 2000-05-10 2003-09-02 Micron Technology, Inc. Flash with consistent latency for read operations
KR100618696B1 (en) * 2004-04-28 2006-09-08 주식회사 하이닉스반도체 Memory device including self-ID number
KR100762259B1 (en) * 2005-09-12 2007-10-01 삼성전자주식회사 Nand flash memory device with burst read latency function
JP5266589B2 (en) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device
US20150095551A1 (en) * 2013-09-30 2015-04-02 Micron Technology, Inc. Volatile memory architecutre in non-volatile memory devices and related controllers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
US5978311A (en) * 1998-03-03 1999-11-02 Micron Technology, Inc. Memory with combined synchronous burst and bus efficient functionality
EP0978842A1 (en) * 1998-08-04 2000-02-09 Samsung Electronics Co., Ltd. Synchronous burst semiconductor memory device
US6044023A (en) * 1995-02-10 2000-03-28 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889726A (en) * 1997-11-17 1999-03-30 Micron Electronics, Inc. Apparatus for providing additional latency for synchronously accessed memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044023A (en) * 1995-02-10 2000-03-28 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
US5978311A (en) * 1998-03-03 1999-11-02 Micron Technology, Inc. Memory with combined synchronous burst and bus efficient functionality
EP0978842A1 (en) * 1998-08-04 2000-02-09 Samsung Electronics Co., Ltd. Synchronous burst semiconductor memory device

Also Published As

Publication number Publication date
JP3631209B2 (en) 2005-03-23
DE10196011B3 (en) 2012-07-26
DE10196011T0 (en)
AU8929101A (en) 2001-10-15
WO2001075896A9 (en) 2002-12-19
KR100508042B1 (en) 2005-08-17
KR20030014380A (en) 2003-02-17
DE10196011T1 (en) 2003-03-13
JP2003529883A (en) 2003-10-07
WO2001075896A2 (en) 2001-10-11

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