JP2003529883A - Flash with read-matched latency - Google Patents

Flash with read-matched latency

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Publication number
JP2003529883A
JP2003529883A JP2001573488A JP2001573488A JP2003529883A JP 2003529883 A JP2003529883 A JP 2003529883A JP 2001573488 A JP2001573488 A JP 2001573488A JP 2001573488 A JP2001573488 A JP 2001573488A JP 2003529883 A JP2003529883 A JP 2003529883A
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Japan
Prior art keywords
data
memory
read
input terminal
status
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JP2001573488A
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Japanese (ja)
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JP3631209B2 (en
Inventor
ルーパーバー、フランキー、エフ.
Original Assignee
マイクロン テクノロジー インコーポレイテッド
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Priority to US19350600P priority Critical
Priority to US60/193,506 priority
Priority to US09/567,733 priority
Priority to US09/567,733 priority patent/US6615307B1/en
Application filed by マイクロン テクノロジー インコーポレイテッド filed Critical マイクロン テクノロジー インコーポレイテッド
Priority to PCT/US2001/010040 priority patent/WO2001075896A2/en
Publication of JP2003529883A publication Critical patent/JP2003529883A/en
Application granted granted Critical
Publication of JP3631209B2 publication Critical patent/JP3631209B2/en
Expired - Fee Related legal-status Critical Current
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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

(57) [Summary] A synchronous flash memory has an array of nonvolatile memory cells. The package configuration of the memory device is compatible with the SDRAM. The memory device has a plurality of selectable transmission paths and includes a pipeline buffer for routing data from an input terminal to an output terminal. Each transmission path requires a predetermined number of clock cycles. The non-volatile synchronous memory includes a circuit for matching the latencies of both types of data by routing both memory data and register data through a pipeline output buffer.

Description

Detailed Description of the Invention

[0001] Technical Field of the Invention The present invention relates to a nonvolatile memory, in particular, relates to non-volatile flash memory synchronous (synchronous).

BACKGROUND OF THE INVENTION Usually, a memory device is provided for the internal storage area of a computer.
The term "memory" refers to an integrated circuit chip used as a data storage medium.
There are several types of memory. For example, RAM (random-access memory) is
Used as the main memory of a computer. The RAM is a readable / writable memory. That is, data can be written to the RAM and data can be read from the RAM. On the other hand, the ROM is a memory that can only read data. Most of the RAMs are volatile, and a holding current is required to maintain the state of storing the content. If the power is turned off, the data recorded in the RAM will be lost.

Most computers have a built-in small capacity ROM in which instruction code groups for starting the computer are recorded. Unlike RAM, writing to ROM is not possible. EEPROM (electrically erasable programmable r
Ead-only memory) is a special non-volatile memory that can erase data (electrically) by applying an electric charge. Originally, as with other ROMs, E
EPROM is not a high speed memory like RAM. The EEPROM includes a large number of memory cells, and each memory cell has a plurality of electrically insulated gates (floating gates). Data is recorded in the memory cell according to the presence / absence of electric charges in the floating gate. Charge is supplied to or removed from the floating gate by programming or erasing.

Further, as another example of the non-volatile memory, there is a flash memory. A flash memory is a type of EEPROM, and data erasing and program updating are performed in block units instead of byte units. Most of recent personal computers record a BIOS in a flash memory chip, and the BIOS can be easily updated when necessary. Such a BIOS is also called a flash BIOS. Flash memory is also often used in modems. By using flash memory, the firmware provided by the modem manufacturer can be updated to support this protocol as new protocols are standardized.

Generally, a flash memory includes a memory array, which is composed of a large number of memory cells designated by a row address and a column address. Each memory cell is provided with a field effect transistor having a floating gate and holding electric charges. These cells are divided into groups on a block-by-block basis. Each cell in the block can be electrically and randomly programmed by applying a charge to the floating gate. The accumulated charges are extracted from the floating gate by the erase process in block units. The cell data is determined by the presence or absence of charges in the floating gate.

Synchronous DRAM (SDRAM) is a DRAM that operates faster than conventional DRAM memories. The SDRAM operates in synchronization with the CPU bus. S
DRAM is about three times as large as conventional FPM (Fast Page Mode) RAM, and EDO (Extend
ed Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM
It operates at 100 MHz, which is about twice the frequency. Although SDRAM can be accessed at high speed, it is volatile. Many computer systems use SDRAM
Although it is designed to operate using a non-volatile memory, use of a non-volatile memory is also expected.

For the above-mentioned reason and the following reasons, in the technical field, SDR is used.
There is a need for non-volatile memory devices that behave similarly to AM. Those reasons will be apparent to those skilled in the art after understanding the contents described in the specification.

SUMMARY OF THE INVENTION The present invention is intended to solve the above-mentioned problems of memory devices, etc., and it will be understood by examining the following description.

In one embodiment, the present invention provides a non-volatile synchronous flash memory compatible with existing SDRAM package pinouts. From the detailed description, it will be apparent that any system designer having knowledge of the SDRAM art can readily implement the present invention to improve system processing.

In one embodiment, a synchronous memory device includes a pipeline buffer having an input terminal and an output terminal. The pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminals to the output terminals, each transmission path requiring a predetermined number of clock cycles. The memory includes a multiplexer circuit connected to the input terminal of the pipeline buffer. The multiplexer circuit has a first input terminal and a second input terminal. The data register circuit is connected to the first input terminal of the multiplexer circuit, and the data read circuit is connected to the second input terminal of the multiplexer circuit. The data read circuit outputs the data read from the memory array of the synchronous memory device.

In another embodiment, a processing system includes a memory controller and a synchronous flash memory device connected to the memory controller. The memory controller receives memory cell data from the synchronous flash memory device after a first predetermined number of clock cycles have elapsed since the memory controller supplied the memory column address. The memory controller also receives status data from the synchronous flash memory device after a second predetermined number of clock cycles has elapsed since the memory controller made a status read request. The first predetermined number of clock cycles and the second predetermined number of clock cycles are the same.

A method for reading data from a synchronous flash memory is provided. The method includes the steps of starting a memory cell read process and outputting memory cell data in response to the memory cell read process. Memory cell data is
It is output to the data connection terminal after a predetermined number of clock cycles have elapsed since the memory cell read process was started. This method includes the steps of starting a status reading process and outputting status data in response to the status reading process. The status data is output to the data connection terminal after a predetermined number of clock cycles have elapsed since the start of the status reading process.

Description of Embodiments of the Invention Embodiments of the present invention will be described in detail with reference to the accompanying drawings. The accompanying drawings form a part of the present specification and illustratively show specific embodiments of the present invention. Each of the embodiments is sufficiently described to enable those skilled in the art to practice the invention. In addition, without departing from the spirit and scope of the present invention, logical, mechanical,
It will be appreciated that the invention may be practiced with electrical modifications. Therefore, the following detailed description should not be construed as limiting. The scope of the invention is defined only by the claims.

The following detailed description is divided into two main items. The first item (Functional Description of Interface) describes in detail compatibility with SDRAM memory. The second item (functional description) defines the functional commands in the flash architecture.

Functional Description of Interface FIG. 1A is a block diagram showing an embodiment of the present invention. Memory device 1
00 includes an array of non-volatile flash memory cells 102. The array is arranged in addressable banks. In the present embodiment, four memory banks 104, 106, 108 and 110 are included in the memory. Each memory bank includes a plurality of addressable sectors of memory cells. The data stored in memory can be accessed by using the location address. This location address is supplied externally and is received by the address register 112. The address is decoded by row address multiplexer 114. Also, the address is decoded by bank control logic 116 and row address latch / decoder 118.
The column address counter / latch 120 combines the received multiple addresses to enable access to the desired column in memory and the column decoder 12
Output to 2. The circuit 124 has a function as an input / output gate, a data mask logic, a read data latch, and a write driver. Data is input through the data input register 126 and output through the data output register 128. The command execution logic 130 controls basic operations of the memory device. The state machine 132 also controls the particular processing performed on the memory array and cells. Further, a status register 134 and an ID register 136 are provided for outputting data.

FIG. 1B shows a connection pin arrangement (input / output connector pin assignment) according to the embodiment of the present invention. The memory package 150 has 54 connection pins. The pin configuration is almost the same as that of the existing SDRAM package. Two connection pins unique to the present invention are RP # 152 and Vccp154. The present invention is SD
Although the same connection pin labels as in RAM are used, the functions of signals input and output through the connection pins in this specification are not the same as those in SDRAM unless otherwise specified. FIG. 1C illustrates a memory package 160 according to one embodiment. The memory package 160 has a bump connection terminal instead of a pin connection terminal. Therefore, the present invention is not limited to any particular packaging configuration.

Before describing the processing characteristics of the memory device, the connection pins and the signals input / output through the connection pins will be described. The input clock terminal is
CLK). The clock signal is driven by the system clock. All the input signals of the synchronous flash memory are sampled at the rising edge (positive edge) of CLK. Further, CLK increments the count value of the internal burst counter and further controls the output register.

The input clock enable (CKE) terminal is used to make the CLK signal input active (HIGH state activated) and inactive (LOW state not activated). By deactivating the clock input,
R-DOWN_STANDBY processing (all memory banks become idle), ACTIVE_POWER-DOWN processing (memory row becomes ACTIVE in any bank), or CLOCK_SUSPEND processing (burst / access is ongoing) become. CKE is in sync except when the memory device is in power down mode. When the memory device is in the power down mode, CKE is in an asynchronous state. The input buffer for CLK and the like is disabled in the power down mode and is in a standby state with low power consumption. CKE may be kept HIGH in the system when power down mode is not required, except when RP # is in deep power down.

A signal for enabling / disabling the command decoder provided in the command execution logic is input to the chip select (CS #) input terminal. If the signal is LOW, the command decoder is valid, and if the signal is HIGH, the command decoder is invalid. That is, if CS # is HIGH, all commands are masked. Furthermore, if there are multiple banks in the system, CS # allows external bank selection. Therefore, CS # can be regarded as a part of the command code. However, this CS # is not mandatory.

Connection terminals RAS #, CAS # and WE # for inputting an input command are (
Together with CAS #, CS #) defines the commands executed by the memory, as described below. The input / output mask (DQM) terminal is used to input a mask signal for write access and output an enable signal for read access. If the DQM sampled during the WRITE cycle was HIGH, the input data is masked. If the DQM sampled during the READ cycle is HIGH, the output buffer goes into the high impedance (High-Z) state after the latency of 2 clocks has elapsed. DQML is
The data terminals DQ0 to DQ7 correspond to the data terminals DQMH to DQ8 to DQ15.
Corresponding to. DQML and DQMH are considered to be in the same state when referred to as DQM.

The address input section (connection terminal) 133 is mainly used for inputting an address signal. In the illustrated embodiment, the memory has 12 lines (A0-A).
11). Further, as will be described later, another signal may be input through the address terminal. To select a location with a memory bank, press A
When a CTIVE command (row address A0 to A11) or a READ / WRITE command (column address A0 to A7) is issued, the signal of the address input section is sampled. The address input section is used for LOAD_COMMAND_REGI which will be described later.
It is also used to input a processing code (OpCode) during the STER processing. In addition, the address lines A0-A11 have LOAD_MODE_REGISTE
Used for entering mode settings during R processing.

The input reset / power down (RP #) terminal 140 is used for performing reset processing and power down processing. In one embodiment, when the device is powered up (initial device power-up), after the RP # goes from LOW to HIGH and before the executable command is issued, due to the initial operation inside the device, A delay time of 100 μs is required. When the RP # signal goes low, the status register is cleared and the state machine (ISM) 132 in the device is set to array read mode. It also puts the device in deep power-down mode. By powering down, all input terminals including CS # 142 are set to "Don't Care", and all outputs are in a High-Z state. R
When the P # signal becomes equal to the VHH voltage (5V), all protection modes are released during the WRITE process and the ERASE process. The RP # signal sets the device protection bit to "1 (protected mode)", but when the RP # signal goes to VHH, each of the block protection bits present in locations 0 and 15 of the 16-bit register is , “0 (non-protected mode)” is set. The protection bit will be described later. In all other processing modes, RP # remains HIGH.

The bank address input terminals BA0 and BA1 are connected to the ACTI
VE command, READ command, WRITE command, or BLOCK_
Defines whether to issue the PROTECT command. The DQ0 to DQ15 terminals 143 are data bus connection terminals used for bidirectional data communication. The VCCQ terminal shown in FIG. 1B is used to supply power to the DQ terminal that is insulated from the VCC terminal so that it is less susceptible to noise interference. In one embodiment,
VCCQ = Vcc, that is, 1.8V ± 0.15V. The VSSQ terminal is used as a ground insulated from the VSS terminal with respect to the DQ terminal so as to be less susceptible to noise interference. The VCC terminal is for supplying power of 3V, for example.
Connection to ground is made through the Vss terminal. In addition, the VCCP terminal 14
Another optional voltage may be supplied through 4. The VCCP terminal is connected to the VCC terminal outside the device, and is used for initial operation of the device, WRITE processing, and ERAS.
E Supply current used for processing. That is, the writing process and the erasing process of the memory device are performed using the voltage supplied through the VCCP terminal, and the other processes are all performed using the voltage supplied through the VCC terminal. The Vccp terminal is connected to the high voltage switch / pump circuit 145.

A more detailed description of the operation of the synchronous flash memory will be given below.
One embodiment of the present invention relates to a programmable ROM that is non-volatile, can electrically erase (flash) data sector by sector. This memory is
67,108,8 configured as 4,194,304 words in 16-bit units
It has a data capacity of 64 bits. Other data capacities are possible and the invention is not limited to the data capacities given as examples. Each of the memory banks consists of four individually erasable blocks. That is, there are 16 blocks in total. To prevent accidental erasing and overwriting processes and to protect important firmware,
The memory includes 16 blocks that can be locked by hardware and software, and each block has a data capacity of 256K words. Since the memory includes four banks, true parallel processing can be realized.

A read access to a bank can be performed when the WRITE process or the ERASE process is being performed on another bank in the background. The synchronous flash memory has a synchronous interface and can register all signals on the rising edge of the clock signal CLK. Also,
Reading of the memory can be performed in burst mode. That is, the memory access begins at the selected location and the number of locations to access is pre-programmed. Memory access is performed according to a pre-programmed sequence. Read access starts with the registration of the ACTIVE command and is continued with the READ command. The address bits registered at the same time as the ACTIVE command are used to select the bank and row to be accessed. Address bits that are registered at the same time as the READ command are used to select the column location and bank that initiates the burst access.

Synchronous flash memory provides a programmable read burst length corresponding to one location, two locations, four locations, eight locations, or a full page. Burst termination may optionally be provided. Moreover, the synchronous flash memory adopts an internal pipeline architecture in order to achieve high-speed processing. The synchronous flash memory operates in a low power memory system, for example, a system driven by 3V. As a memory operation mode, a deep power down mode is provided as a power saving standby mode. All inputs and outputs are LVTTL (
low voltage transistor-transistor logic) compatible. The synchronous flash memory can greatly improve the flash processing performance. here,
The flash processing performance includes the ability to transfer data at high speed while automatically generating the column address, and the ability to randomly switch the column address for each clock cycle during the burst access period.

In general, the synchronous flash memory is driven by a low voltage and has the same structure as a DRAM having a plurality of banks. Each of the banks is composed of a plurality of rows and a plurality of columns. The synchronous flash memory is initialized before performing normal processing. The device initialization, register definition, command contents, and device operation will be described in detail below.

The synchronous flash is powered up and initialized in a predetermined manner. When power is supplied to VCC, VCCQ, and VCCP (at the same time), the clock signal stabilizes and RP # 140 goes from the LOW state to the HIGH state. A delay time of, for example, 100 μs is required after the RP # shifts to the HIGH state until the initialization inside the device is completed. After the delay time has elapsed, the memory is in the array read mode, ready for programming the mode register or executing commands. After the initial programming of the non-volatile mode register (NV mode register) 147, the content is automatically loaded into the volatile mode register during the initialization process. The device powers up in a pre-programmed state and does not need to reload the non-volatile mode register 147 again before issuing a process command. This will be described later.

The mode register 148 is used to define a specific processing mode of the synchronous flash memory. This definition includes the burst length, as shown in FIG.
This includes selection of burst type, CAS latency, and processing mode. The mode register programs based on the LOAD_MODE_RESISTOR command and holds the stored information until reprogramming is performed. The contents of the mode register may be copied to NV mode register 147. N
The mode register 148 is automatically loaded during the initialization process based on the setting of the V mode register. Details of the ERASE_NVMODE_REGISTER command and the WRITE_NVMODE_REGISTER command will be described later. Those skilled in the art will understand that in the SDRAM, the mode register needs to be externally loaded after each initialization process. According to the present invention, the default mode setting is registered in the NV mode register 147. The contents of the NV mode register are copied to the volatile mode register 148 and accessed while each operation is performed in memory.

Mode register bits M0-M2 define the burst length. Mode register bit M3 defines the burst type (sequential, interleaved). Mode register bits M4-6 define CAS latency. Mode register bits M7 and M8 define the processing mode. Mode register bit M
9 is set to 1. Mode register bits M10 and M11 are reserved in this embodiment. In the present embodiment, since the WRITE burst is not executed, M9 is set to logic 1 and the write access is performed in one location (non-burst). The mode register needs to be loaded when all banks are idle. The controller has to wait a predetermined time to start the subsequent processing.

Read access to the synchronous flash memory is performed in burst mode. The burst length is programmable as shown in Table 1. Burst length defines the maximum number of column locations that can be automatically accessed by a given READ command. Whether the burst type is sequential or interleaved, it has burst lengths corresponding to one location, two locations, four locations, and eight locations. If the burst type is sequential, the burst length corresponding to a full page can be used. If the burst length is full page, the BURST_TERMINATE command may be used to create any burst length. That is, the burst length can be customized by selectively ending the burst. RE
When the AD command is issued, it is possible to select a block including a number of columns corresponding to the burst length. All accesses performed in this burst mode are performed within the selected block. That is, the block is continuously accessed until the boundary is reached. When the burst length is set to 2, a block is independently selected by A1 to A7. If the burst length is set to 4, A2
A block is selected by ~ A7. When the burst length is set to 8, the block is selected by A3 to A7. The remaining lower address bits (including the least significant bit) are used to select the starting position within the block. A full page burst will continuously access within that page until the boundary is reached.

The access made within a given burst is programmed by bit M3 into a burst type of sequential or interleaved. The access order within the burst is determined by the burst length, burst type, and starting column address, as shown in Table 1.

[0033]

[Table 1]

The CAS (Column Address Strobe) latency indicates a delay time in clock cycles until the first output data can be used at the DQ terminal after the READ command is registered. The latency can be set to 1, 2, or 3 clock cycles. For example, if a READ command is registered at clock edge n and the latency is m clocks, then data is available at clock edge n + m. The DQ connection unit starts driving the data at the clock edge one cycle before (n + m−1), and when the access time is appropriate, the clock edge n +
Valid data are obtained with m. For example, assuming that the clock cycle time is set so that the access time is appropriate, when the READ command is registered at T0 and the latency is 2 clocks, the DQ is as shown in FIG.
Data driving is started after T1 and valid data is obtained at T2. FIG. 3 shows an example of the operation cycle when the latency settings of different clocks are used. The normal processing mode is selected by setting M7 and M8 to zero. A preprogrammed burst length is applied to the READ burst.

The following truth table shows the memory processing commands of the present invention in more detail.
Each command and truth table 2 will be described.

[0036]

[Table 2]

[0037]

[Table 3]

The COMMAND_INHIBIT function inhibits execution of new commands by the synchronous flash memory regardless of whether the CLK signal is valid. Although the synchronous flash memory is in the non-selected state, it does not affect the processing already being executed.

The NO_OPERATION (NOP) command is used to execute NOP on the synchronous flash memory selected with CS # set to LOW. Execution of NOP can prevent undesired commands from being registered during the idle state or the standby state. However, it does not affect the processing that is already being executed.

Data for the mode register is loaded through the input terminals A0 to A11. LOAD_MODE only when all array banks are idle
After the _REGISTER command is issued and a predetermined delay time (MRD) has elapsed, the command for the process to be executed next is issued. NV mode register 14
The data held by 7 is stored at the time of initialization processing at power-on (upon power-up i) unless dynamically changed by the LOAD_MODE_REGISTER command.
nitialization), the mode register 148 is automatically loaded with default data.

The ACTIVE command opens (activates) a row in a particular array bank so that it can be accessed. The bank is selected by the input values from the input terminals BA0 and BA1, and the row is selected by the address input from the input terminals A0 to A11. The next ACTIVE command, power down command, or
This row is active for access until the RESET command is registered.

The READ command is used to initiate a read access to the active row in burst mode. The bank is selected by the input values from the input terminals BA0 and BA1, and the starting column location is selected by the address input from the input terminals A0 to A7. The read data on the DQ terminal depends on the logic level on the data mask (DQM) input terminal two clocks before. When the registration of the given DQM signal is HIGH, the corresponding DQ terminal after two clocks becomes High-Z (high impedance). When the registration of the given DQM signal is LOW, the DQ terminal holds valid data. Therefore, the output data can be masked using the DQM input terminal during the read process.

The WRITE command is used to initiate a write access at one location in the active row. It is necessary to issue the WRITE_SETUP command before issuing the WRITE command. Input terminals BA0, B
The bank is selected by the input value from A1 and the column location is selected by the address input from the input terminals A0 to A7. Input data on the DQ terminal is written to the memory array. The input data is D that appears at the same time as the input data.
It depends on the logic level of the QM input. If the registration of the given DQM signal is LOW, the corresponding data is written in the memory. If the registration of the DQM signal is HIGH, the input of the corresponding data is ignored and the WRITE process at the word / column location that is the write target is not executed. WRI
When the TE command is issued and the registration of the DQM signal is HIGH, NO
It is considered that the P command has been issued.

Although the ACTIVE_TERMINATE command is not essential for the synchronous flash memory, it can be used to end the read process in the same manner as the PRECHARGE command of SDRAM. ACTIVE_T
The ERMINATE command is issued to terminate the BURST_READ that is being executed, but may or may not be issued to a specific bank.

The BURST_TERMINATE command is used to truncate a burst over a fixed length or full page. BURST_
The READ command registered immediately before the TERMINATE command is registered is truncated. The BURST_TERMINATE command is not issued for a particular bank.

The load command register process is used to start output of a flash memory control command to the command execution logic (CEL) 130. CE
L receives and decodes commands to the device. This command controls the operation of the internal state machine (ISM) 132 and the read path (that is, the memory array 102, the ID register 136, or the status register 134).

A READ command or W for a bank in the synchronous flash memory
The row to be processed in this bank must be "opened" (activated) before the RITE command is issued. This is C, as shown in FIG.
This is performed by the ACTIVE command defined by S #, WE #, RAS #, and CAS #, and both banks and rows to be activated are selected.

After opening the line by issuing the ACTIVE command, the READ command and the WRITE command are issued to this line. The time until the READ command or the WRITE command is issued is determined based on a predetermined period (tRCD specification). The value obtained by dividing tRCD (MIN) by the clock cycle is rounded up to an integer.
Based on this integer, the first clock edge at which the READ command or WRITE command is issued after the ACTIVE command is issued is obtained. For example, if the specification of tRCD is 30 ns and the clock is 90 MHZ (11.11 ns clock cycle), the calculated value is 2.7 clocks and is rounded up to "3". In this case, that is, in the case of 2 <tRCD (MIN) / tCK ≦ 3 is shown in FIG. 5 (when the specification conditions of tRCD are different, the same unit can be used to convert the unit of time into a clock cycle. it can).

Issuing the next ACTIVE command for different rows in the same bank
If the minimum interval between consecutive ACTIVE commands for this bank is defined by tRCD, it can be done without closing the previously activated row.

The next ACTIVE command for another bank can be issued while the first bank is being accessed. Therefore, the total overhead in row access can be reduced. Sequential ACTIVE for different banks
The minimum command interval is defined by the period tRCD.

The READ burst is started by the READ command defined by CS #, WE #, RAS #, and CAS # shown in FIG. The READ command selects the starting column and bank address. During the READ burst, RE
After issuing the AD command and after the CAS latency has elapsed, a valid data-out element from the address of the starting column is available. Each subsequent data output element is valid on the next positive clock edge, respectively. After the burst ends, if no other command is started, the DQ terminal is in the HIGH-Z state. Full page bursts run continuously until the end (column 0 at the end of the page).
Return to, processing continues). The data from the READ burst is truncate when the next READ command is issued. The data from the next READ command immediately follows the data from the fixed length READ burst.
In either case, a continuous data flow is maintained. The first data element of the new burst follows the last data element of the finished burst, or, if the burst is longer than a fixed length (truncated halfway), after the last desired data element. . A new READ command is issued x cycles before the clock edge when the last desired data element is valid. x is one less than the CAS latency. In FIG. 7, when the CAS latency is 1, 2, and 3,
Data element n + 3 is the end of four bursts or the end of a burst longer than a fixed length. Since the synchronous flash memory adopts the pipeline architecture, it does not require the 2n rule unlike the prefetch architecture. The READ command can be started in any clock cycle after the last READ command. The highest speed random read access within a page is performed as shown in FIG. Each subsequent READ process may be performed on a different bank.

The data from the READ burst is truncated by the next WRITE command. It is necessary to execute WRITE_SETUP before the WRITE command. Immediately after the data from the fixed length READ burst, the next WR
The data from the ITE command follows. The WRITE command is subject to bus turnaround restrictions. If I / O contention can be avoided, REA
The WRITE process starts on the clock edge immediately after the last (last desired) data element from the D burst. Depending on the design of the system, the device that drives the input data may become Low-Z before the DQ terminal of the synchronous flash memory becomes High-Z. In this case, a delay of at least one cycle occurs between the last read data and the WRITE command.

The DQM input is used to avoid the I / O contention shown in FIG. DQM
The signal is asserted (HIGH) at least 2 clocks before the WRITE command (DQM latency for the output buffer is 2 clocks), and READ
The data output from is suppressed. When the WRITE command is registered, the DQ terminal becomes High-Z (or High-Z regardless of the state of the DQM signal.
Maintain the state of). Prior to the WRITE command (the DQM latency for the input buffer is zero clock), the DQM signal must be deasserted and the write data masked. In FIG. 9, the clock frequency is NOP.
The case where the bus contention is set to be avoided without adding a cycle is shown.

A fixed-length or full-page READ burst may be sent to ACTIVE_TERMIN
It is truncated by either an ATE command (which may or may not be for a particular bank) or a BURST_TERMINATE command (not for a particular bank). ACTIVE
_TERMINATE command and BURST_TERMINATE command
Issued x cycles before the clock edge when the last desired data element is valid. x is 1 less than the CAS latency. This is shown in FIG. 10 for each of the different CAS latencies. Data element n + 3 may be the last desired data element of the four bursts, or the last desired data element in a burst longer than a fixed length.

WRITE processing at one location is performed by CS #, WE #, R shown in FIG.
It is started by the WRITE command defined by AS # and CAS #.
The WRITE command selects the starting column and bank address. WRIT
Once the E command is registered, RE as defined by truth tables 4 and 5
The AD command is executed. An example is shown in FIG. WRI during WRITE processing
A valid data input (data-in) is registered at the same time as the TE command.

Unlike SDRAM, synchronous flash memory does not require a PRECHARGE command to deactivate an open row in a particular bank or in all banks. ACTIVE_TERMIN
The ATE command is similar to the BURST_TERMINATE command, except that A
The CTIVE_TERMINATE command may or may not be for a particular bank. ACTIVE_TERMINA
If the input A10 is asserted and becomes HIGH during the execution of the TE command,
BURST_READ ends in any bank. ACTIVE_TER
If the input A10 is LOW while executing the MINATE command, BA0, BA1
Specifies which bank to end. ACTIVE_TERMINA
TE is considered to be the NOP for banks not addressed by A10, BA0, BA1.

NOP or COMMAND_INHIB when no access is made
Power down occurs when the clock enable CKE matching IT is registered LOW. When a power down occurs, the input buffer and output buffer are deactivated except for CKE after the processing by the internal state machine including the WRITE processing. That is, the standby state of the power saving mode is set.

The power-down state ends when NOP or COMMAND_INHIBIT is registered and CKE becomes HIGH (satisfies tCKS) at a desired clock edge. FIG. 13 shows an example of the power down process.

When the CKE terminal is registered to LOW during execution of column access / burst, the clock suspend mode is entered. In clock suspend mode, the internal clock becomes inactive and the synchronous logic "freezes." When CKE is sampled LOW at the rising edge of each clock,
The next rising edge of the internal clock is suspended. When the internal clock edge is suspended, commands and data held in the input terminals are ignored. As long as the clock is suspended, as shown in the example of FIG. 14, the data held by the DQ terminal maintains its driven state and the burst counter is not incremented. The clock suspend mode ends when the CKE terminal is registered as HIGH, and the processing by the internal clock is restarted at the next rising edge of the clock.

Burst read / single write mode is the default mode in one embodiment. All WRITE commands generate an access (single burst) at a single column location, and READ commands generate an access to each column according to a pre-programmed burst length, sequence. The following truth table 3 shows the memory processing using the CKE signal.

[0061]

[Table 4]

[0062]

[Table 5]

[0063]

[Table 6]

Functional Description The synchronous flash memory has many functions and is suitable for storing codes on the SDRAM bus and for applications using the XIP (execute in place) technology. The memory array is subdivided into individual erase blocks. The data held in each block can be erased without affecting the data held in other blocks. Reading, writing, and erasing of these memory blocks can be performed by issuing commands to the command execution logic (CEL) 130. CEL is an internal state machine (ISM) 13
Control the processing of 2. CEL is ERASE_NVMODE_REGISTER
Processing, WRITE_NVMODE_REGISTER processing, WRITE processing, B
LOCK_ERASE processing, BLOCK_PROTECT processing, DEVICE_
Full control over the PROTECT, UNPROTECT_ALL_BLOCKS, and VERIFY processes. The ISM 132 protects each memory location from being overerased and optimizes each memory location for maximum retention of data. In addition, ISM greatly simplifies the control required to write a device within the system or by an external programmer.

The synchronous flash memory is composed of 16 separate erasable blocks. The data held in a memory block can be partially erased without affecting the data held in other memory blocks. The memory block may be protected by hardware from accidental erasure or writing. When protecting a block, it is necessary to drive the voltage of the RP # terminal to VHH (relatively high voltage) before the data in the block is modified. Blocks with a capacity of 256K words at locations 0 and 15 may be provided with additional hardware protection. PRO for these blocks
Once the TECT command is executed, UNPROTECT_ALL_BLOC
By the KS command, if RP # is not VHH, protection of all blocks except location 0 and location 15 is released. This enhances security for critical code during firmware updates within the system, even in the unlikely event of a power failure or system reset.

Initialization at power-on, ERASE processing, WRITE processing and PROTE
The timing of the CT process is simplified by using ISM which controls all programming algorithms in the memory array. The ISM protects the data by preventing over-erasure and optimizes the write margin for each cell. During the WRITE process, the ISM automatically increments and monitors the number of WRITE process attempts, verifies the write margin in each memory cell, and updates the ISM status register. When performing the BLOCK_ERASE process, the ISM automatically overwrites the entire address block to prevent over-erase, increments and monitors the number of WRITE process attempts, and checks the ISM.
Set a bit in the status register.

The 8-bit ISM status register 134 is used by the external processor 200 as a WR.
Monitors the status of ISM during ITE processing, ERASE processing, and PROTECT processing. Of the 8-bit status register, 1 bit (SR7) is set and cleared (set cancellation) completely by the ISM. This bit is
Indicates whether the ISM is busy with the ERASE process, the WRITE process, or the PROTECT process. Further, other error information, that is, write protection block error, erase non-protection all block error, and device protection error are set by another three bits (SR3, SR4, SR5). Status register bit SR
0, SR1 and SR2 provide detailed information on the processing of the ISM being executed. The user can confirm whether the ISM processing at the device level is in progress or the ISM processing at the bank level is in progress, and also which bank is controlled by the ISM. These 6 bits (SR3 to SR5) are
Must be cleared by the host system. The status register will be described in more detail with reference to Table 2.

The CEL 130 receives and decodes commands to the device. Each command controls the ISM's processing and read path (ie, memory array, device configuration, or status register). When ISM is active, a command is issued to CEL.

In order to enhance the power saving effect, the synchronous flash is compatible with an extremely low current deep power down mode. In order to enter this mode, it is necessary to set the RP # terminal 140 (reset / power down) to VSS ± 0.2V. To avoid accidental RESET, the device will not enter reset mode unless RP # is maintained at Vss for 100 ns. If RP # is maintained at Vss, the device enters deep power down mode. When RP # changes from LOW to HIGH after the device has entered deep power-down mode, the device boot initialization sequence is performed, as outlined herein. Even if RP # changes from LOW to HIGH after entering the reset mode, if the deep power down mode is not entered, a delay time of 1 μs is required before issuing an executable command. When the device enters deep power down mode, all buffers except the RP # buffer are disabled and the current draw is low, for example 50 μA maximum at 3.3V VCC. The input to RP # must be maintained at Vss while in deep power down mode. R
When the ESET mode is entered, the status register 134 is cleared and the ISM13
2 is set to array read mode.

According to the synchronous flash memory architecture, when the data in each sector is erased, it does not affect other parts of the array. The array is divided into 16 addressable "blocks" which can be individually erased. Data can be erased in blocks rather than the entire array, increasing overall device durability and system flexibility. ERAS
Only the E function and the BLOCK_PROTECT function are executed in block units. The 16 addressable blocks are in four banks 104, 106, 10
Equally divided into 8,110. That is, each bank 104, 106, 108, 110 consists of four blocks. For four banks, one can read and the other can write simultaneously. WRIT by ISM for a bank
The READ process can be performed on another bank during the E process or the ERASE process. By polling the status register 134, it can be determined for which bank the ISM process is being performed. Synchronous flash memory is an ISM that performs a single background process.
Equipped with. This ISM has initialization processing at power-on, ERASE processing, WR
Controls ITE and PROTECT processing. In any case
Only one process by ISM can be executed. However, READ
Other specific commands, including processing, can be executed while performing ISM processing. The processing command controlled by the ISM is bank-level processing or device-level processing. The WRITE process and the ERASE process are ISM processes performed at the bank level. When the ISM processing performed at the bank level is started, invalid data is output in any of the locations of the READ processing in this bank, but when the READ processing is performed in another bank. , The array is read. When the READ_STATUS_REGISTER command is executed, the content held by the status register 134 is output. The ISM status bit indicates the end of ISM processing (SR7 = 1).
When the ISM process is complete, the bank automatically enters the array read mode. ER
ASE_NVMODE_REGISTER processing, WRITE_NVMODER
EGISTER processing, BLOCK_PROTECT processing, DEVICE_PRO
The TECT process and UNPROTECT_ALL_BLOCKS process are ISM processes performed at the device level. Once the ISM processing performed at the device level is started, the content held by the array is output regardless of which bank the READ processing is performed. The READ_STATUS_REGISTER command is issued to determine the end of ISM processing. When SR7 = 1, the ISM processing ends and the next ISM processing starts. To protect the block data by preventing unintended ERASE or WRITE processing by the hardware circuit, drive RP # to VHH before the WRITE or ERASE processing as described below. There is a need to.

Blocks of data may be protected by hardware in order to increase security for the most important parts of the firmware. RP # must be maintained at VHH while the WRITE or ERASE process is being performed on the block protected by the hardware, that is, until the WRITE or ERASE process is completed. If RP # = VHH,
WRITE or ERASE processing for protected blocks is prohibited,
A write error or erase error will occur. The blocks at locations 0 and 15 have additional hardware protection to protect against unexpected WRITE or ERASE operations. In this embodiment, these blocks are
When RP # = VHH is not established, the protection cannot be released by software based on the issue of the UNPROTECT_ALL_BLOCKS command. The protection status of a block can be confirmed by issuing a READ_STATUS_REGISTER command and reading the protection bit of the block. Further, in order to protect the block, it is necessary to issue a 3-cycle command sequence to the target block address.

The synchronous flash memory supports READ processing in three different modes. Data is created from one of the memory array, status register, or device configuration register by the READ process according to the mode. The READ process for the device configuration register or status register is performed after the LCR-ACTIVE cycle. The burst length of data out is defined by the mode register setting.
READ treatment after LCR-ACTIVE cycle, or LCR-ACTIV
The array is read by a READ operation that does not require E cycles. However, since there are some variations in the read operation, they will be described in the following items.

Execution of the READ command for a bank outputs the contents of the memory array. While the WRITE process or the ERASE process by the ISM is being performed, invalid data is output even if the READ process is performed to any location in the bank under the control of the ISM. Upon termination of the RESET process, the device automatically enters the array read mode.

In order to execute the READ processing of the status register 134, the same input sequence as that at the time of reading the array is required, but LCR_READ_STATUS
The S_REGISTER (70H) cycle must precede the ACTIVE READ cycle. The burst length of the data output by the status register is defined by the mode register 148. The content held by the status register is updated and latched at the next rising edge of the clock after the CAS latency has elapsed. The device automatically enters the array read mode and is ready for the next READ process.

Reading the device configuration register 136 requires the same input sequence as reading the status register, but a specific address must be designated. WE # must be HIGH, DQM and C
S # must be LOW. To read the manufacturer compatible ID, the address must be designated as 000000H. To read the device ID, the address must be specified as 000001H. The block protection bit is read at the third address location within each erase block (xx0002H) and the device protection bit is located at location 00000003H.
Read from.

The DQ terminal is also used to input data to the array. The address terminal is used to specify an address location, or LOAD_COMMAND_
Used to enter commands to CEL during the REGISTER cycle. By the command input, an 8-bit command is issued to the CEL to control the processing mode of the device. The WRITE process is used to input data to the memory array. Both input types will be described below.

In order to execute the command input, DQM must be LOW and CS #
And WE # must also be LOW. The address terminal and the DQ terminal are used to input each command. Address terminals that are not used to enter commands are "don't care" and must remain in state. The 8-bit command is an input to DQ0 to DQ7 or A0 to A7 and is latched at the rising edge of the clock.

The WRITE operation on the memory array sets the desired bit to a logical 0, but the bit set to a logical 0 cannot be changed to a logical 1.
Setting any bit to a logic one erases the data in the entire block.
In order to execute the WRITE processing, DOQ must be LOW and CS
# And WE # must also be LOW. Also, VCCP must be held at VCC. To write to a protected block, use RP #
Must be VHH. A write address is designated by A0 to A11, and the data to be written in the array is input to the DQ terminal. Data and addresses are latched on the rising edge of the clock. Before the WRITE process,
A WRITE_SETUP command needs to be issued.

In order to simplify the writing of the memory block, the ISM of the synchronous flash memory controls all the internal algorithms of the WRITE cycle and the ERASE cycle. An 8-bit command set is used to control the device. Truth Tables 1 and 2 list the valid commands.

By polling the 8-bit ISM status register 134 (Table 2), ERASE_NVMODE_REGISTER processing, WRIT
E_NVMODE_REGISTER processing, WRITE processing, ERASE processing,
It is checked whether the BLOCK_PROTECT process, the DEVICE_PROTECT process, or the UNPROTECT_ALL_BLOCKS process has ended, and whether an error has occurred during these processes. The end of the ISM process is monitored by issuing the READ_STATUS_REGISTER (70H) command. The contents of the status register are output to DQ0 to DQ7 and, after the CAS latency has elapsed, are updated by the fixed burst length defined by the setting of the mode register at the rising edge of the next clock. The ISM process ends when SR7 = 1. All blocks defined by bits are set by ISM, but only the ISM status bits are IS
Reset by M. Erase / unprotected block, write / protected block,
Device protection must be cleared by the CLEAR_STATUS_REGISTER (50H) command. This allows the user to select when to poll to clear the status register. For example, the host system may check the status register after multiple WRITE operations, rather than checking the status register after each WRITE operation. The status register is also cleared by asserting the RP # signal and powering down the device.

[0081]

[Table 7]

The device ID, manufacturer compatible ID, device protection status, and block protection status are all READ_DEVICE_CONFIGURAT
It is read by issuing the ION (90H) command. A specific address must be asserted to read the desired register. Details on the configuration registers 136 for various devices are shown in Table 3.

[0083]

[Table 8]

It is also possible to issue a command for changing the processing mode of the device. In each mode, processing unique to that mode is performed. In some modes, it is necessary to write a series of commands before executing the process. The characteristics of each mode will be described below. Truth tables 1 and 2 are a list of command sequences required to perform the desired processing. With the function of simultaneously performing reading and writing, it is possible to perform reading processing to another bank while performing writing processing or erasing processing on a bank which is background processing. In the writing process, the LCR-ACTIVE-WRITE command sequence described in the truth table 2 must be completed in consecutive clock cycles. However, in order to simplify the processing of the synchronous flash controller, the NOP command or COMMAND_INHIBIT command is issued in an unlimited number during this command sequence. Furthermore, in order to enhance the data protection function, these command sequences must be assigned to the same bank address for three cycles. If the bank address is changed during the LCR-ACTIVE-WRITE command sequence, or if the command sequences are not continuous (during the command sequence, except for the NOP command and COMMAND_INHIBIT command which are allowed to issue commands). If a command is issued), the write status bit and erase status bit (SR4 and SR5) are set and the processing is prohibited.

After power-up (power-up), the synchronous flash memory is initialized before the processing command is issued to the device. After power is applied to VCC, VCCQ, and VCCP (simultaneously), the clock stabilizes and RP
# Changes from LOW to HIGH. After RP # shifts to HIGH, a delay time (100 μs in one embodiment) is required to complete initialization inside the device.
Delay time) is required. When the device initialization is complete, the device is in array read mode and an executable command is issued to the device.

To read each of the device ID, manufacturer compatible ID, device protection bit, and block protection bit, READ_DEVICE_CONFIGURA
A TION (90H) command is issued. In this mode, a specific address is designated to read out the desired information. Manufacturer compatible ID is 0000
It is read at 00H. The device ID is read as 000001H. The manufacturer compatibility and the device ID are output to DQ0 to DQ7. The device protection bit is read at 000003H. Each of the block protection bits is read at the third address location (xx0002H) in each block. The device protection bit and the block protection bit are output to DQ0.

In order to input data to the array, it is necessary to issue three consecutive commands at consecutive clock edges (the NOP command and the COMMAND_INHIBIT command can be issued during each cycle). Exist). In the first cycle, for A0-A7, LOAD_COMMAND_REG
The ISTER command is issued together with the WRITE_SETUP command (40H), and bank addresses are issued to BA0 and BA1. In the next cycle, the ACTIVE command is issued, the row address becomes active, and the bank address is confirmed. The third cycle is a WRITE command,
The starting column, bank address and data are issued. The ISM status bit is set at the next clock edge after the CAS latency has elapsed. ISM is W
While executing the RITE process, the ISM status bit (SR7) becomes 0. Under the control of ISM, invalid data is created when a READ process is performed on a bank. When the ISM status bit (SR7) is set to logic 1,
After the WRITE processing is completed, this bank is in the array read mode, and the command can be executed. Even when writing to a block protected by hardware, RP # is set to VH before executing the third cycle, WRITE processing.
It must be set to H and RP will be used until WRITE processing by ISM is completed.
# Must be held at VHH. LCR-ACT in consecutive cycles
If the IVE-WRITE command sequence has not ended, or if the bank address has changed in any of the three cycles, the write status bit and erase status bit (SR4 and SR5) are set.
When the ISM starts the WRITE processing, the WRITE processing is not stopped unless the RESET processing is performed or the power down is performed.
In either case, if the RESET processing is performed or the power down is performed, the data being written may be destroyed.

Executing the ERASE sequence sets all bits in the block to logic ones. The command sequence required to execute the ERASE process is WRI.
It is similar to that for executing the TE process. In order to prevent accidental block erase and increase security, the ERASE process of a block must be initiated by issuing three consecutive commands on consecutive clock edges. In the first cycle, LOAD_COMM for A0-A7
AND_REGISTER command is ERASE_SETUP command (20H
) And the bank address of the block to be erased is issued to BA0 and BA1. In the next cycle, the ACTIVE command is issued,
The address of the block to be erased is designated by A10, A11, BA0, BA1. In the third cycle, a WRITE command is issued, during which DQ
The ERASE_CONFIRM command (D0H) is issued to 0 to DQ7, and the bank address is reissued. The ISM status bit is set at the next clock edge after the CAS latency has elapsed. ERASE_CONFIRM
After the command (D0H) is issued, the ISM starts the ERASE processing of the addressed block. When the READ process is performed on the bank in which the block whose address is specified exists, invalid data is output. ERAS
When the E process is completed, the bank is placed in the array read mode and the command can be executed. Even when erasing a block protected by hardware, RP # needs to be set to VHH before executing the third cycle of WRITE processing, and the ERASE processing by ISM ends (SR7 = 1). ) Up to RP
# Must be held at VHH. LCR-ACT in continuous cycle
When the IVE-WRITE command sequence is not completed (the NOP command and COMMAND_INHIBIT command are allowed to be issued during each cycle), or when the bank address is changed in one or more command cycles. The write status bit and the erase status bit (SR4 and SR5) are set, and the processing is prohibited.

The contents of the mode register 148 are changed to WRITE_NVMODE_REGIS.
It may be copied to the NV mode register by the TER command. Before writing to the NV mode register, ERASE_NVMODE_REGIST
It is necessary to end the ER command sequence and set all bits in the NV mode register to logic one. The command sequence required to execute the ERASE_NVMODE_REGISTER process and the WRITE_NVMODE_REGISTER process is the same as that for executing the WRITE process. E
RASE_NVMODE_REGISTER processing and WRITE_NVMOD
L_ACTIVE-WR required to end E_REGISTER processing
Detailed information about the ITE command is given in Truth Table 2. ERAS
E_NVMODE_REGISTER command sequence or WRITE_N
After the WRITE cycle of the VMODEREGISTER command sequence is registered, a READ command is issued to the array. The new WRITE process is not permitted until the ISM process currently being executed ends and SR7 = 1.

Executing the BLOCK_PROTECT sequence can provide first level software / hardware protection for a given block.
The memory has a 16-bit register that protects 16 blocks with one bit. In addition, the memory includes a register that provides a device bit for protecting the data of the entire device by preventing a write process and an erase process. BLOCK_
The command sequence required to execute the PROTECT process is similar to that for executing the WRITE process. In order to prevent unexpected block erases and increase security, the BLOCK_PROTECT process must be initiated by issuing three consecutive commands. In the first cycle, the LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with the PROTECT_SETUP command (60H), and BA0
, BA1 the bank address of the block to be protected is issued. In the next cycle, the ACTIVE command is issued, the row of the block to be protected becomes active and the bank address is confirmed. In the third cycle,
A WRITE command is issued, and BLOCK is issued to DQ0 to DQ7 during that time.
The _PROTECT_CONFIRM command (01H) is issued and the bank address is reissued. After the CAS latency has elapsed, I will be output at the next clock edge.
The SM status bit is set. Then, the ISM starts the PROTECT process. If the LCR-ACTIVE-WRITE command sequence is not completed in consecutive cycles (NOP command and COMMAND_INHIBIT command is allowed to be issued between cycles), or
When the bank address is changed, the WRITE status bit and the erase status bit (SR4 and SR5) are set, and the processing is prohibited. IS
When the M status bit (SR7) is set to logic 1, the PROTECT process is complete, the bank is in array read mode and the command can be executed. Once the block protection bit is set to 1 (protected), UNPROTECT
This protection bit cannot be changed except by resetting it to 0 by the _ALL_BLOCKS command. The UNPROTECT_ALL_BLOCKS command sequence is similar to the BLOCK_PROTECT command, but the third
In the cycle, the WRITE command is UNPROTECT_ALL_BLOC
Issued with the KS_CONFIRM command (D0H) to specify the address as "don't care". The truth table 2 also includes other information. The blocks at locations 0 and 15 are even more secure. Once the block protection bits for locations 0 and 15 are set to 1 (protected),
Each bit sets RP # to VHH before the third cycle of UNPROTECT processing.
To the BLOCK_PROTECT process or UNPROTECT ALL_B
The bit is not reset to 0 unless it is held at VHH until the LOCKS process is completed (SR7 = 1). In addition, if the device protection bit is set,
Bring RP # to VHH and BLOCK_PROTECT before the third cycle
VHH until processing or UNPROTECT_ALL_BLOCKS processing is completed
Need to hold. To confirm the protection status of the block, READ_DE
This is done by issuing the VICE_CONFIGURATION command (90H).

Executing the DEVICE_PROTECT sequence sets the device protection bits to 1 and prevents modification of the block protection bits. DEVICE_P
The command sequence required to execute the ROTECT process is similar to that for executing the WRITE process. Three consecutive command cycles are required to start the DEVICE_PROTECT sequence. In the first cycle, the LOAD_COMMAND_REGISTER command is issued to A0 to A7 together with the PROTECT_SETUP command (60H), and BA0,
A bank address is issued to BA1. The bank address is "don't care", but the same bank address must be used for all three cycles. The next command is ACTIVE. The third cycle is W
It is a RITE cycle. D for DQ0 to DQ7 during the WRITE cycle
The EVICE_PROTECT command (F1H) is issued, and RP # becomes VHH. The ISM status bit is set at the next clock edge after the CAS latency has elapsed. It becomes possible to issue executable commands to the device. RP # is VHH until WRITE processing is completed (SR7 = 1)
Must be held in. It is not allowed to execute a new WRITE process until the ISM process currently being executed is completed. Once the device protection bit is set to 1, unless the RP # goes to VHH, BLOCK_PROTECT processing and BL
OCK_UNPROTECT processing cannot be performed. The device protection bit does not affect the WRITE process or the ERASE process. More detailed information about the block protection process and device protection process is shown in Table 4.

[0092]

[Table 9]

After the ISM status bit (SR7) is set, the device / bank (SR
0), device protection (SR3), bank A0 (SR1), bank A1 (SR2)
, Write / protect block (SR4) and erase / unprotect (SR5) status bits are checked. If one of the status bits of SR3, SR4, SR5 or a combination (some) of these status bits is set, an error occurs during processing. ISM is SR3, SR4, SR
You cannot reset the 5 bit. In order to clear these bits, it is necessary to issue the CLEAR_STATUS_REGISTER command (50H). Table 5 shows errors due to the combination of SR3, SR4, and SR5.

[0094]

[Table 10]

Synchronous flash memory is designed and manufactured to meet the high demands of code and data storage. In order to secure such a level of reliability, VCC is set to V during WRITE cycles or ERASE cycles.
must be held at cc. If the processing is executed without satisfying this constraint, the number of WRITE cycles executed in the device and the ERA
The number of SE cycles is reduced. Each block is designed and manufactured so that it can be written / erased at least 100,000 times.

The synchronous flash memory has some power saving functions, and this power saving function can be used in the array read mode to save power. Deep power down mode can be implemented by bringing RP # to VSS ± 0.2V. In this mode, the amount of current (ICC) is small, for example, 50 μA at maximum. When CS # goes HIGH, the device enters active standby mode. Even in this mode, the current is low and the amount of current (ICC)
Is, for example, 30 mA at maximum. If CS # goes HIGH during a write, erase, or protect process, the ISM continues the WRITE process and the device consumes active Iccp power until the process is complete.

FIG. 16 is a flowchart of a self-timed write sequence according to an embodiment of the present invention. This sequence includes loading the command register (code 40H), receiving active commands and row addresses, receiving write commands and column addresses. Then, in this sequence, the status register is polled to determine whether the writing is completed. Status register bit 7 (SR7) is monitored by polling to determine if status register bit 7 is set to one. Further, as an option, the status check may be executed. When the write process is complete, the array enters array read mode.

FIG. 17 shows a flowchart of a complete read status check sequence according to an embodiment of the present invention. In this sequence, status register bit 4 (SR4) is checked to determine if it is set to zero. S
If R4 is 1, it is determined that an error has occurred during the writing process. Then, in this sequence, the status register bit 3 (SR3) is checked and 0
Is set to. If SR3 is 1, it is determined that an invalid write error has occurred during the write process.

FIG. 18 shows a flowchart of a self-synchronous block erase sequence according to an embodiment of the present invention. This sequence involves loading the command register (code 20H), receiving the active command and row address. The memory then determines if the block is protected. If the block is not protected, the memory performs a write process (D0H) on the block and monitors the status register to determine if the process is complete. Further, as an option, the status check may be executed. When the erase process is complete, the memory enters the array read mode. If the block is protected,
The erasing process cannot be executed unless the RP # signal is at the high voltage (VHH).

FIG. 19 shows a flowchart of a complete block erase status check sequence according to an embodiment of the present invention. In this sequence, the status register is monitored to see if a command sequence error has occurred (S
R4 = 1 or SR5 = 1). If SR3 is set to 1, an invalid erase error or a non-protection error (protection violation error) occurs. If SR5 is set to 1, a block erase error or a non-protection error (protection violation error) occurs.

FIG. 20 shows a flowchart of a block protection sequence according to an embodiment of the present invention. This sequence is for loading the command register (code 60H),
Includes receipt of active commands and row addresses. The memory then determines if the block is protected. If the block is not protected, the memory performs a write process (01H) on the block, monitors the status register, and checks whether the process is complete. Further, as an option, the status check may be executed. When the block protection process is complete, the memory enters the array read mode. If the block is protected, the erase process cannot be performed unless the RP # signal is at high voltage (VHH).

FIG. 21 shows a flowchart of a complete block status check sequence according to an embodiment of the present invention. In this sequence, status register bits 3, 4, and 5 are monitored to determine if an error was detected.

FIG. 22 shows a flowchart of a device protection sequence according to an embodiment of the present invention. This sequence is for loading the command register (code 60H),
Includes receipt of active commands and row addresses. And the memory is R
It is determined whether P # is VHH. The memory is a writing process (F1
H) is executed, the status register is monitored, and it is checked whether the writing process is completed. Further, as an option, the status check may be executed. When the device protection process ends, the memory enters the array read mode.

FIG. 23 shows a flowchart of the block protection release sequence according to the embodiment of the present invention. This sequence is for loading the command register (code 60H
), Receiving active commands and line addresses. The memory then determines if the memory device is protected. If not, the memory determines if the boot location (blocks 0 and 15) is protected. If neither block is protected, the memory performs a write operation (D0H) on the block and monitors the status register to check if the write operation is complete. As an option, a status check may be performed. When the all block protection release processing is completed, the memory enters the array read mode. If the device is protected, the erase process cannot be performed unless the RP # signal is at high voltage (VHH). Similarly, if each boot location is protected, the memory determines if all blocks should be unprotected.

FIG. 24 shows the timing of processing for initializing and loading the mode register. The mode register is programmed by issuing a load mode register command and issuing a processing code (opcode) to the address line.
The opcode is loaded into the mode register. As mentioned above, the contents of the non-volatile mode register may be automatically loaded into the mode register on power-up and no load mode register processing is required.

FIG. 25 shows the timing of the clock suspend mode process, and FIG. 26 shows the timing of another burst read process. FIG. 27 shows the timing when the bank read access is alternately performed. Here, an active command is required to change the bank address. FIG. 28 shows a full page burst read process. Full page bursts require the issuance of an end command without being self-synchronizing.

FIG. 29 shows the timing of the reading process using the data mask signal. D
The QM signal is used to mask the data output so that Dout m + 1 is not output to the DQ terminal.

FIG. 30 shows the timing when the read process is performed on different banks after the write process is performed. In this process, the write process is performed on the bank a, and then the read process is performed on the bank b. The same row is accessed in each bank.

FIG. 31 shows the timing when the read process is performed on the same bank after the write process is performed. In this process, the write process is performed on the bank a, and then the read process is performed on the bank a. In the read process another row is accessed and the memory has to wait for the write process to finish. This is the case in the read process as shown in FIG.
That is, it differs from the case where the delay time due to the writing process does not occur at the start of the reading process.

Latency Matched in All Read Processes With the synchronous flash of the present invention, memory contents can be read basically in the same manner as SDRAM. That is, this synchronous flash memory has a read latency. In the conventional flash memory, the reading process of the status register 282, the intelligent identifier register, etc. may be executed. The data held by the status register 282 is the multiplexer circuit 2 that controls the data traffic according to the processing mode.
Read using 80. Such a prior art system is shown in FIG. The data in the status register 282 is output from the multiplexer circuit 280. The second input terminal of the multiplexer circuit can receive data from the pipeline buffer 284 and the memory array read circuit 286. An output buffer circuit 288 is connected to the multiplexer circuit in order to output data from the multiplexer circuit to the DQ connection terminal.

A problem arises when such a conventional system is applied to a synchronous flash. If the processing mode is different depending on whether array reading or register reading is performed, the data read latency is different, so there is a high possibility that bus contention will occur when reading the data from the register, causing a problem with the bus controller. Sometimes. That is, the output data from the multiplexer circuit may have a read latency that does not match the read latency of the data in the memory.

The present invention has a different output design than the conventional one. As shown in FIG. 33, the flash memory of the present invention includes a multiplexer circuit 302 connected to the input terminal of the pipeline buffer 304. In one embodiment, the output buffer has three pipeline paths. The pipeline path is selected according to the clock latency (1, 2, or 3) during the reading process. The memory array read circuit 124, the status register 134, and the identification (configuration) register 136 are connected to the multiplexer circuit 302. The multiplexer circuit is connected to the pipeline circuit and the output buffer circuit 306.
Therefore, both memory array data and register data are processed through the selected pipeline path. In this way, the data from the registers will always have the same clock latency as the array data. Therefore, according to the present invention, bus conflicts are less likely to occur due to register read processing.

Conclusion In this specification, a synchronous flash memory including an array of non-volatile memory cells has been described. The package configuration of the memory device is compatible with SDRAM. The memory device includes a pipeline buffer having a plurality of selectable transmission paths and routing data from an input terminal to an output terminal. Each transmission path requires a certain number of clock cycles. The non-volatile synchronous memory includes a circuit that matches the latency of both types of data by routing both memory data and register data through a pipeline output buffer. In one embodiment, this circuit includes a multiplexer circuit connected to the input terminal of the pipeline buffer.
The data register circuit is connected to the first input terminal of the multiplexer circuit, and the data read circuit is connected to the second input terminal of the multiplexer circuit. The data read circuit outputs the data read from the memory array of the synchronous memory device.

[Brief description of drawings]

1A is a block diagram showing a synchronous flash memory according to the present invention, FIG. 1B is a diagram showing terminal connections of an integrated circuit according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram showing an arrangement of bump grid arrays of an integrated circuit according to an embodiment of the present invention.

[Fig. 2]   It is explanatory drawing which shows the mode register which concerns on one embodiment of this invention.

FIG. 3 is an operation explanatory diagram showing a read process when the CAS latency is 1, 2, and 3 clock cycles.

FIG. 4 is an operation explanatory diagram showing a process of activating a specific row of the bank of the memory according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram showing a timing between an activation command and a read command or a write command.

[Figure 6]   It is explanatory drawing which shows a read command.

FIG. 7 is a diagram showing timings of continuous read bursts according to the embodiment of the present invention.

FIG. 8 is a diagram showing timing of random read access within a page according to an embodiment of the present invention.

[Figure 9]   It is a figure which shows the timing of the writing process performed following a reading process.

FIG. 10 is a diagram showing a timing at which the read burst process ends using the burst terminate command in the embodiment of the present invention.

FIG. 11   It is explanatory drawing which shows a write command.

[Fig. 12]   It is a figure which shows the timing of the read-out process performed following a write-in process.

[Fig. 13]   It is a figure which shows the timing of the power-down process which concerns on one embodiment of this invention.

FIG. 14 is a diagram showing a timing of a clock suspend process at the time of burst read.

FIG. 15 is an explanatory diagram showing a memory address map in the embodiment in which the memory has two boot sectors.

FIG. 16 is a flowchart showing a self-synchronous write sequence according to an embodiment of the present invention.

FIG. 17 is a flowchart showing a complete write status check sequence according to an embodiment of the present invention.

FIG. 18 is a flowchart showing a self-synchronization erasing sequence according to an embodiment of the present invention.

FIG. 19 is a flowchart showing a complete block erase status check sequence according to an embodiment of the present invention.

FIG. 20 is a flowchart showing a block protection sequence according to an embodiment of the present invention.

FIG. 21 is a flowchart showing a complete block status check sequence according to an embodiment of the present invention.

FIG. 22 is a flowchart showing a device protection sequence according to one embodiment of the present invention.

FIG. 23 is a flowchart showing a block protection release sequence according to an embodiment of the present invention.

FIG. 24   It is a figure which shows the initialization of a mode register, and the timing of load processing.

FIG. 25   It is a figure which shows the timing of a clock suspend mode process.

FIG. 26   It is a figure which shows the timing of a burst read process.

FIG. 27   It is a figure which shows the timing which performs bank read access by turns.

FIG. 28   It is a figure which shows the timing of a full page burst read process.

FIG. 29 is a diagram showing a timing of burst read processing performed using a data mask signal.

FIG. 30 is a diagram showing a timing of performing a read process on a different bank subsequent to the read process.

FIG. 31 is a diagram showing a timing of performing a read process on the same bank subsequent to the write process.

FIG. 32   It is a figure which shows the conventional register circuit.

FIG. 33   It is a figure which shows one Embodiment of the register | resistor of this invention.

─────────────────────────────────────────────────── ─── Continued front page    (81) Designated countries EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, I T, LU, MC, NL, PT, SE, TR), OA (BF , BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, G M, KE, LS, MW, MZ, SD, SL, SZ, TZ , UG, ZW), EA (AM, AZ, BY, KG, KZ, MD, RU, TJ, TM), AE, AG, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, B Z, CA, CH, CN, CO, CR, CU, CZ, DE , DK, DM, DZ, EE, ES, FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, I S, JP, KE, KG, KP, KR, KZ, LC, LK , LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, MZ, NO, NZ, PL, P T, RO, RU, SD, SE, SG, SI, SK, SL , TJ, TM, TR, TT, TZ, UA, UG, UZ, VN, YU, ZA, ZW F term (reference) 5B025 AA01 AD01 AD05 AD15 AE00                       AE05                 5B060 CC02

Claims (27)

[Claims]
1. A pipeline buffer having an input terminal and an output terminal; a multiplexer circuit having a first input terminal and a second input terminal and connected to the input terminal of the pipeline buffer; In a synchronous memory device including a data register circuit connected to the first input terminal of a multiplexer circuit, and a data read circuit connected to the second input terminal of the multiplexer circuit, the pipeline buffer includes: A plurality of selectable transmission paths for routing data from the input terminal to the output terminal, each transmission path requiring a predetermined number of clock cycles; A thin-film device characterized by outputting data read from a memory array of a memory device. Russia eggplant memory device.
2. The synchronous memory device according to claim 1, wherein the pipeline buffer has a clock latency of 1 during read processing,
A synchronous memory device having three transmission paths that can be selected to be two or three.
3. The synchronous memory device according to claim 1, wherein the data register circuit includes a status register that holds status data.
4. The synchronous memory device according to claim 3, wherein the status data includes an activation status of a state machine in the synchronous memory device, a memory array bank status, and processing error data. And a synchronous memory device.
5. The synchronous memory device according to claim 1, wherein the array of memory cells is an array of non-volatile memory cells.
6. An array of non-volatile memory cells, a pipeline buffer having an input terminal and an output terminal, a first input terminal and a second input terminal, and the input terminal of the pipeline buffer. A synchronous memory device including a connected multiplexer circuit, a data register circuit connected to the first input terminal of the multiplexer circuit, and a data read circuit connected to the second input terminal of the multiplexer circuit. In, the pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminal to the output terminal, each transmission path requires a predetermined number of clock cycles, The data read circuit outputs the data read from the nonvolatile memory array, and outputs the data. The synchronous memory device, wherein data from a register circuit and data from the data read circuit are transmitted through the pipeline buffer circuit using one of the plurality of selectable transmission paths.
7. The synchronous memory device according to claim 6, wherein the pipeline buffer has a clock latency of 1 during read processing.
A synchronous memory device having three transmission paths that can be selected to be two or three.
8. A processing system including a memory controller and a synchronous flash memory device connected to the memory controller, wherein the synchronous flash memory device comprises an array of non-volatile memory cells, an input terminal and data. A pipeline buffer having an output terminal; a multiplexer circuit having a first input terminal and a second input terminal connected to the input terminal of the pipeline buffer; and the first input of the multiplexer circuit. A status register circuit connected to the terminal; and a memory read circuit connected to the second input terminal of the multiplexer circuit, wherein the pipeline buffer routes data from the input terminal to the data output terminal. Multiple selectable transmission patterns for Each transmission path requires a predetermined number of clock cycles, the data output terminal of the pipeline buffer is connected to the memory controller via a data bus, and the data read circuit is non-volatile. Data read from an array of memory cells is provided, and data from the status register circuit and data from the memory read circuit is transferred to the pipeline buffer circuit using one of the plurality of selectable transmission paths. A processing system characterized by being transmitted through.
9. The processing system according to claim 8, wherein the plurality of selectable transmission paths have a transmission delay of 1 clock cycle, a transmission delay of 2 clock cycles, and a transmission delay of 3 clock cycles. A processing system including a transmission path.
10. A processing system including a memory controller and a synchronous flash memory device connected to the memory controller, wherein the memory controller has a first predetermined value after the memory controller supplies a memory column address. After passing a certain number of clock cycles, the memory cell data is received from the synchronous flash memory device, and the memory controller passes a second predetermined number of clock cycles after the memory controller issues a status read request. After that, status data is received from the synchronous flash memory device, and the first predetermined number of clock cycles and the second predetermined number of clock cycles are the same.
11. The processing system according to claim 10, wherein the synchronous flash memory comprises an array of non-volatile memory cells, a pipeline buffer having an input terminal and a data output terminal, a first input terminal and a first input terminal. A multiplexer circuit having two input terminals and connected to the input terminal of the pipeline buffer; a status register circuit connected to the first input terminal of the multiplexer circuit; and a second register circuit of the multiplexer circuit. And a memory read circuit connected to an input terminal of the pipeline buffer, wherein the pipeline buffer has a plurality of selectable transmission paths for routing data from the input terminal to the data output terminal. The path requires a certain number of clock cycles and the pipeline buffer A data output terminal is connected to the memory controller via a data bus, the data read circuit supplies data read from the array of nonvolatile memory cells, and the data from the status register circuit and the memory read A processing system wherein data from a circuit is transmitted through the pipeline buffer circuit using one of the plurality of selectable transmission paths.
12. The processing system according to claim 10, wherein the first and second predetermined numbers of clock cycles are 1 clock cycle and 2 clock cycles.
A processing system comprising three clock cycles.
13. A synchronous flash including an array of non-volatile memory cells and a pipeline buffer which is connected to an external data connection terminal and supplies memory read data in response to a read request and status register data in response to a status request. In the memory, the memory read data is supplied to the external data connection terminal after a predetermined number of clock cycles have passed since the read request was made, and the predetermined number of clock cycles have passed since the status request was made. Then, the status register data is supplied to the external data connection terminal, and the memory read data and the status register data have the same clock latency, and the synchronous flash memory device.
14. The synchronous flash memory device according to claim 13, wherein the multiplexer circuit includes a first input terminal and a second input terminal and is connected to an input terminal of the pipeline buffer, and the multiplexer circuit. Further comprising a status register circuit connected to the first input terminal of the array read circuit and an array read circuit connected to the second input terminal of the multiplexer circuit, wherein the data read circuit is configured to read the data read from the memory array. A synchronous flash memory device characterized by supplying
15. The synchronous flash memory device according to claim 13, wherein the predetermined number of clock cycles includes one clock cycle, two clock cycles, and three clock cycles.
16. A step of starting a memory cell read process, and outputting memory cell data by the memory cell read process to a data connection terminal after a predetermined number of clock cycles have elapsed after starting the memory cell read process. And a step of starting the status reading process, and a step of outputting the status data by the status reading process to the data connection terminal after the predetermined number of clock cycles have elapsed from the start of the status reading process. A method of reading data from a synchronous flash memory device, comprising:
17. The method according to claim 16, wherein the step of outputting the memory cell data outputs the memory cell data to an input terminal of a pipeline buffer during the predetermined number of clock cycles. To read data from a synchronous flash memory device.
18. The method according to claim 16, wherein the step of outputting the status data outputs the status data to an input terminal of a pipeline buffer during the predetermined number of clock cycles, and outputs the status data. A method of reading data from a synchronous flash memory device, comprising the step of transmitting through a pipeline buffer.
19. The method according to claim 16, wherein the step of outputting the memory cell data outputs the memory cell data to an input terminal of a pipeline buffer for the predetermined number of clock cycles. Transmitting the status data through the pipeline buffer, wherein outputting the status data includes outputting the status data to the input terminal of the pipeline buffer for the predetermined number of clock cycles. To read data from a synchronous flash memory device.
20. The method according to claim 19, wherein a path for the memory cell data and the status data to the pipeline buffer is selectively established by a multiplexer circuit. How to read.
21. The method of claim 16, wherein the predetermined number of clock cycles includes 1 clock cycle, 2 clock cycles, 3 clock cycles.
22. A path for receiving memory data or status data through an input terminal of a pipeline buffer, a step of transmitting the memory cell data or the status data through the pipeline buffer, the memory cell data or Outputting the status data to an external data connection terminal. A method of reading data from a synchronous memory device.
23. The method according to claim 22, wherein the step of establishing a path for receiving the memory cell data or the status data reads the memory cell data and outputs the memory cell data to a first input terminal of a multiplexer circuit. Establishing a path through which the status data is read and receiving the status data through a second input terminal of the multiplexer circuit; and establishing a path through which the status data is received through the second input terminal of the multiplexer circuit. 2. A method of reading data from a synchronous memory device, comprising the step of selectively establishing a path between any one of the two input terminals and the pipeline buffer.
24. The method according to claim 22, wherein the pipeline buffer has a plurality of selectable transmission paths, and data is read from a synchronous memory device.
25. The method according to claim 24, wherein the plurality of selectable transmission paths have a delay time of 1 clock cycle, a delay time of 2 clock cycles, and a delay time of 3 clock cycles. A method of reading data from a synchronous memory device, which comprises a transmission path.
26. A step of reading memory cell data and establishing a path for transmitting the memory cell data to a first input terminal of a multiplexer circuit; reading status data from a status register and transmitting the status data to the multiplexer circuit. Establishing a path for transmission to a second input terminal, and selectively establishing a path between one of the first input terminal and the second input terminal of the multiplexer circuit and an input terminal of a pipeline buffer. A method of reading data from a synchronous memory device, the method comprising: a pipeline buffer having a plurality of selectable transmission paths, and transmitting either the memory cell data or the status data through the pipeline buffer. , External data connection end Method of reading data from the synchronous device and outputting to.
27. The method of claim 26, wherein the plurality of selectable transmission paths have a delay time of 1 clock cycle, a delay time of 2 clock cycles, and a delay time of 3 clock cycles. A method of reading data from a synchronous memory device, which comprises a transmission path.
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