WO2001075896A2 - Flash with consistent latency for read operations - Google Patents

Flash with consistent latency for read operations Download PDF

Info

Publication number
WO2001075896A2
WO2001075896A2 PCT/US2001/010040 US0110040W WO0175896A2 WO 2001075896 A2 WO2001075896 A2 WO 2001075896A2 US 0110040 W US0110040 W US 0110040W WO 0175896 A2 WO0175896 A2 WO 0175896A2
Authority
WO
WIPO (PCT)
Prior art keywords
data
memory
read
input
status
Prior art date
Application number
PCT/US2001/010040
Other languages
French (fr)
Other versions
WO2001075896A9 (en
WO2001075896A3 (en
Inventor
Frankie F. Roohparvar
Original Assignee
Micron Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US19350600P priority Critical
Priority to US60/193,506 priority
Priority to US09/567,733 priority
Priority to US09/567,733 priority patent/US6615307B1/en
Application filed by Micron Technology, Inc. filed Critical Micron Technology, Inc.
Publication of WO2001075896A2 publication Critical patent/WO2001075896A2/en
Publication of WO2001075896A3 publication Critical patent/WO2001075896A3/en
Publication of WO2001075896A9 publication Critical patent/WO2001075896A9/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106Data output latches
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1615Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement using a concurrent pipeline structrure
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1694Configuration of memory controller to different memory types
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1045Read-write mode select circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087Data input latches
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10Aspects relating to interfaces of memory device to external buses
    • G11C2207/105Aspects related to pads, pins or terminals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/2281Timing of a read operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2207/00Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22Control and timing of internal memory operations
    • G11C2207/229Timing of a write operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires predetermined number of clock cycles. The non-volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data.

Description

FLASH WITH CONSISTENT LATENCY FOR READ OPERATIONS

Technical Field of the Invention

The present invention relates generally to non-volatile memory devices and in particular the present invention relates to a synchronous non-volatile flash memory.

Background of the Invention

Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost. Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.

Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.

A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.

A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.

For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a manner similar to SDRAM operation.

Summary of the Invention The above-mentioned problems with memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. hi one embodiment, the present invention provides a non- volatile synchronous flash memory that is compatible with existing SDRAM package pin assignments. It will be apparent from reading the detailed description that system designers with knowledge, in SDRAM applications could easily implement the present invention to improve system operation.

In one embodiment, a synchronous memory device comprises a pipeline buffer having an input connection and an output connection. The pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles. The memory includes a multiplex circuit coupled to the input of the pipeline buffer. The multiplex circuit has a first and second input. A data register circuit is coupled to the first input of the multiplex circuit, and a data read circuit is coupled to the second input of the multiplex circuit. The data read circuit provides output data read from a memory array of the synchronous memory device.

In another embodiment, a processing system comprises a memory controller, and a synchronous flash memory device coupled to the memory controller. The memory controller receives memory cell data from the synchronous flash memory device a first predetermined number of clock cycles after a memory column address has been provided by the memory controller. The memory controller also receives status data from the synchronous flash memory device a second predetermined number of clock cycles after a status read request has been provided by the memory controller. The first and second predetermined number of clock cycles are equal. A method of reading from a synchronous flash memory device is provided. The method comprises initiating a memory cell read operation, and outputting memory cell data in response to the memory cell read operation. The memory cell data is output on data connections a predetermined number of clock cycles after the memory cell read operation is initiated. The method includes initiating a status read operation, and outputting status data in response to the status read operation. The status data is output on the data connections the predetermined number of clock cycles after the status read operation is initiated.

Brief Description of the Drawings Figure IA is a block diagram of a synchronous flash memory of the present invention;

Figure IB is an integrated circuit pin interconnect diagram of one embodiment of the present invention;

Figure IC is an integrated circuit interconnect bump grid array diagram of one embodiment of the present invention; Figure 2 illustrates a mode register of one embodiment of the present invention;

Figure 3 illustrates read operations having a CAS latency of one, two and three clock cycles;

Figure 4 illustrates activating a specific row in a bank of the memory of one embodiment of the present invention; Figure 5 illustrates timing between an active command and a read or write command; Figure 6 illustrates a read command;

Figure 7 illustrates timing for consecutive read bursts of one embodiment of the present invention;

Figure 8 illustrates random read accesses within a page of one embodiment of the present invention;

Figure 9 illustrates a read operation followed by a write operation;

Figure 10 illustrates read burst operation that are terminated using a burst terminate command according to one embodiment of the present invention;

Figure 11 illustrates a write command; Figure 12 illustrates a write followed by a read operation;

Figure 13 illustrates a power-down operation of one embodiment of the present invention;

Figure 14 illustrates a clock suspend operation during a burst read;

Figure 15 illustrates a memory address map of one embodiment of the memory having two boot sectors; Figure 16 is a flow chart of a self-timed write sequence according to one embodiment of the present invention;

Figure 17 is a flow chart of a complete write status-check sequence according to one embodiment of the present invention;

Figure 18 is a flow chart of a self-timed block erase sequence according to one embodiment of the present invention;

Figure 19 is a flow chart of a complete block erase status-check sequence according to one embodiment of the present invention;

Figure 20 is a flow chart of a block protect sequence according to one embodiment of the present invention; Figure 21 is a flow chart of a complete block status-check sequence according to one embodiment of the present invention;

Figure 22 is a flow chart of a device protect sequence according to one embodiment of the present invention;

Figure 23 is a flow chart of a block unprotect sequence according to one embodiment of the present invention; Figure 24 illustrates the timing of an initialize and load mode register operation; Figure 25 illustrates the timing of a clock suspend mode operation; Figure 26 illustrates the timing of a burst read operation; Figure 27 illustrates the timing of alternating bank read accesses; Figure 28 illustrates the timing of a full-page burst read operation;

Figure 29 illustrates the timing of a burst read operation using a data mask signal; Figure 30 illustrates the timing of a write operation followed by a read to a different bank; Figure 31 illustrates the timing of a write operation followed by a read to the same bank; Figure 32 illustrates a prior art register circuit; and Figure 33 illustrates an embodiment of a register of the present invention.

Detailed Description of the Invention

In the following detailed description of present embodiments, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration specific embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the claims.

The following detailed description is divided into two major sections. The first section is an Interface Functional Description that details compatibility with an SDRAM memory. The • second major section is a Functional Description that specifies flash architecture functional commands.

Interface Functional Description Referring to Figure IA, a block diagram of one embodiment of the present invention is described. The memory device 100 includes an array of non-volatile flash memory cells 102. The array is arranged in a plurality of addressable banks. In one embodiment, the memory contains four memory banks 104, 106, 108 and 110. Each memory bank contains addressable sectors of memory cells. The data stored in the memory can be accessed using externally provided location addresses received by address register 112. The addresses are decoded using row address multiplexer circuitry 114. The addresses are also decoded using bank control logic 116 and row address latch and decode circuitry 118. To access an appropriate column of the memory, column address counter and latch circuitry 120 couples the received addresses to column decode circuitry 122. Circuit 124 provides input/output gating, data mask logic, read data latch circuitry and write driver circuitry. Data is input through data input registers 126 and output through data output registers 128. Command execution logic 130 is provided to control the basic operations of the memory device. A state machine 132 is also provided to control specific operations performed on the memory arrays and cells. A status register 134 and an identification register 136 can also be provided to output data.

Figure IB illustrates an interconnect pin assignment of one embodiment of the present invention. The memory package 150 has 54 interconnect pins. The pin configuration is substantially similar to available SDRAM packages. Two interconnects specific to the present invention are RP# 152 and Nccp 154. Although the present invention may share interconnect labels that are appear the same as SDRAM's, the function of the signals provided on the interconnects are described herein and should not be equated to SDRAM's unless set forth herein. Figure IC illustrates one embodiment of a memory package 160 that has bump connections instead of the pin connections of Figure IC. The present invention, therefore, is not limited to a specific package configuration.

Prior to describing the operational features of the memory device, a more detailed description of the interconnect pins and their respective signals is provided. The input clock connection is used to provide a clock signal (CLK). The clock signal can be driven by a system clock, and all synchronous flash memory input signals are sampled on the positive edge of CLK. CLK also increments an internal burst counter and controls the output registers.

The input clock enable (CKE) connection is used to activate (HIGH state) and deactivates (LOW state) the CLK signal input. Deactivating the clock input provides POWER-DOWN and STANDBY operation (where all memory banks are idle), ACTINE POWER-DOWN (a memory row is ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down modes to provide low standby power. CKE may be tied HIGH in systems where power-down modes (other than RP# deep power-down) are not required. The chip select (CS#) input connection provides a signal to enable (registered LOW) and disable (registered HIGH) a command decoder provided in the command execution logic. All commands are masked when CS# is registered HIGH. Further, CS# provides for external bank selection on systems with multiple banks, and CS# can be considered part of the command code; but may not be necessary. The input command input connections for RAS#, CAS#, and WE# (along with CAS#,

CS#) define a command that is to be executed by the memory, as described in detail below. The input/output mask (DQM) connections are used to provide input mask signals for write accesses and an output enable signal for read accesses. Input data is masked when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a high impedance (High-Z) state (after a two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to data connections DQ0-DQ7 and DQMH corresponds to data connections DQ8-DQ15. DQML and DQMH are considered to be the same state when referenced as DQM.

Address inputs 133 are primarily used to provide address signals. In the illustrated embodiment the memory has 12 lines (AO-Al 1). Other signals can be provided on the address connections, as described below. The address inputs are sampled during an ACTINE command (row-address AO-Al 1) and a READ/WRITE command (column-address A0-A7) to select one location in a respective memory bank. The address inputs are also used to provide an operating code (OpCode) during a LOAD COMMAND REGISTER operation, explained below. Address lines AO-Al 1 are also used to input mode settings during a LOAD MODE REGISTER operation. An input reset/power-down (RP#) connection 140 is used for reset and power-down operations. Upon initial device power-up, a lOOμs delay after RP# has transitioned from LOW to HIGH is required in one embodiment for internal device initialization, prior to issuing an executable command. The RP# signal clears the status register, sets the internal state machine (ISM) 132 to an array read mode, and places the device in a deep power-down mode when LOW. During power down, all input connections, including CS# 142, are "Don't Care" and all outputs are placed in a High-Z state. When the RP# signal is equal to a NHH voltage (5N), all protection modes are ignored during WRITE and ERASE. The RP# signal also allows a device protect bit to be set to 1 (protected) and allows block protect bits of a 16 bit register, at locations 0 and 15 to be set to 0 (unprotected) when brought to NHH. The protect bits are described in more detail below. RP# is held HIGH during all other modes of operation.

Bank address input connections, BAO and BAl define which bank an ACTINE, READ, WRITE, or BLOCK PROTECT command is being applied. The DQ0-DQ15 connections 143 are data bus connections used for bi-directional data communication. Referring to Figure IB, a NCCQ connection is used to provide isolated power to the DQ connections to improved noise immunity. In one embodiment, NCCQ = Ncc or 1.8N ±0.15N. The NSSQ connection is used to isolated ground to DQs for improved noise immunity. The NCC connection provides a power supply, such as 3N. A ground connection is provided through the Nss connection. Another optional voltage is provided on the NCCP connection 144. The NCCP connection can be tied externally to NCC, and sources current during device initialization, WRITE and ERASE operations. That is, writing or erasing to the memory device can be performed using a NCCP voltage, while all other operations can be performed with a NCC voltage. The Veep connection is coupled to a high voltage switch/pump circuit 145.

The following sections provide a more detailed description of the operation of the synchronous flash memory. One embodiment of the present invention is a nonvolatile, electrically sector- erasable (Flash), programmable read-only memory containing 67, 108,864 bits organized as 4,194,304 words by 16 bits. Other population densities are contemplated, and the present invention is not limited to the example density. Each memory bank is organized into four independently erasable blocks (16 total). To ensure that critical firmware is protected from accidental erasure or overwrite, the memory can include sixteen 256K-word hardware and software lockable blocks. The memory's four-bank architecture supports true concurrent operations.

A read access to any bank can occur simultaneously with a background WRITE or ERASE operation to any other bank. The synchronous flash memory has a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read accesses to the memory can be burst oriented. That is, memory accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Read accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ command are used to select the starting column location and bank for the burst access.

The synchronous flash memory provides for programmable read burst lengths of 1 , 2, 4 or 8 locations, or the full page, with a burst terminate option. Further, the synchronous flash memory uses an internal pipelined architecture to achieve high-speed operation.

The synchronous flash memory can operate in low-power memory systems, such as systems operating on three volts. A deep power-down mode is provided, along with a power- saving standby mode. All inputs and outputs are low voltage transistor-transistor logic (LNTTL) compatible. The synchronous flash memory offers substantial advances in Flash operating performance, including the ability to synchronously burst data at a high data rate with automatic column address generation and the capability to randomly change column addresses on each clock cycle during a burst access.

In general, the synchronous flash memory is configured similar to a multi-bank DRAM that operates at low voltage and includes a synchronous interface. Each of the banks is organized into rows and columns. Prior to normal operation, the synchronous flash memory is initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

The synchronous flash is powered up and initialized in a predefined manner. After power is applied to NCC, NCCQ and NCCP (simultaneously), and the clock signal is stable, RP# 140 is brought from a LOW state to a HIGH state. A delay, such as a lOOμs delay, is needed after RP# transitions HIGH in order to complete internal device initialization. After the delay time has passed, the memory is placed in an array read mode and is ready for Mode Register programming or an executable command. After initial programming of a non-volatile mode register 147 (ΝNMode Register), the contents are automatically loaded into a volatile Mode Register 148 during the initialization. The device will power up in a programmed state and will not require reloading of the non-volatile mode register 147 prior to issuing operational commands. This is explained in greater detail below. The Mode Register 148 is used to define the specific mode of operation of the synchronous flash memory. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 2. The Mode Register is programmed via a LOAD MODE REGISTER command and retains stored information until it is reprogrammed. The contents of the Mode Register may be copied into the NVMode Register 147. The NVMode Register settings automatically load the Mode Register 148 during initialization. Details on ERASE NVMODE REGISTER and WRITE NVMODE REGISTER command sequences are provided below. Those skilled in the art will recognize that an SDRAM requires that a mode register must be externally loaded during each initialization operation. The present invention allows a default mode to be stored in the NV mode register 147. The contents of the NV mode register are then copied into a volatile mode register 148 for access during memory operations.

Mode Register bits M0-M2 specify a burst length, M3 specifies a burst type (sequential or interleaved), M4-M6 specify a CAS latency, M7 and M8 specify a operating mode, M9 is set to one, and M10 and Mi l are reserved in this embodiment. Because WRITE bursts are not currently implemented, M9 is set to a logic one and write accesses are single location (non-burst) accesses. The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating a subsequent operation.

Read accesses to the synchronous flash memory can be burst oriented, with the burst length being programmable, as shown in Table 1. The burst length determines the maximum number of column locations that can be automatically accessed for a given READ command. Burst lengths of 1, 2, 4, or 8 locations are available for both sequential and the interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst can be used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths that is, a burst can be selectively terminated to provide custom length bursts. When a READ command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two, by A2- A7 when the burst length is set to four, and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

TABLE 1 BURST DEFINITION

Figure imgf000012_0001
Column Address Strobe (CAS) latency is a delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data on the DQ connections. The latency can be set to one, two or three clocks cycles. For example, if a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + in. The DQ connections will start driving data as a result of the clock edge one cycle earlier (n + m - 1) and, provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at TO, and the latency is programmed to two clocks, the DQs will start driving after TI and the data will be valid by T2, as shown in Figure 3. Figure 3 illustrates example operating frequencies at which different clock latency setting can be used. The normal operating mode is selected by setting M7 and M8 to zero, and the programmed burst length applies to READ bursts.

The following truth tables provide more detail on the operation commands of an embodiment of the memory of the present invention. An explanation is provided herein of the commands and follows Truth Table 2.

TRUTH TABLE 1 Interface Commands and DQM Operation

Figure imgf000013_0001
Figure imgf000014_0001

TRUTH TABLE 2 Flash Memory Command Sequences

Figure imgf000014_0002
Figure imgf000015_0001

The COMMAND INHIBIT function prevents new commands from being executed by the synchronous flash memory, regardless of whether the CLK signal is enabled. The synchronous flash memory is effectively deselected, but operations already in progress are not affected.

The NO OPERATION (NOP) command is used to perform a NOP to the synchronous flash memory that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states, and operations already in progress are not affected.

The mode register data is loaded via inputs AO-Al 1. The LOAD MODE REGISTER command can only be issued when all array banks are idle, and a subsequent executable command cannot be issued until a predetermined time delay (MRD) is met. The data in the NVMode Register 147 is automatically loaded into the Mode Register 148 upon power-up initialization and is the default data unless dynamically changed with the LOAD MODE REGISTER command.

An ACTIVE command is used to open (or activate) a row in a particular array bank for a subsequent access. The value on the BAO, BAl inputs selects the bank, and the address provided on inputs AO-Al 1 selects the row. This row remains active for accesses until the next ACTINE command, power-down or RESET.

The READ command is used to initiate a burst read access to an active row. The value on the BAO, BAl inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. Read data appears on the DQs subject to the logic level on the data mask (DQM) input that was present two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z (high impedance) two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data. Thus, the DQM input can be used to mask output data during a read operation. A WRITE command is used to initiate a single-location write access on an active row. A

WRITE command must be preceded by a WRITE SETUP command. The value on the BAO, BAl inputs selects the bank, and the address provided on inputs A0-A7 selects a column location. Input data appearing on the DQs is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that word/column location. A WRITE command with DQM HIGH is considered a NOP.

An ACTIVE TERMINATE command is not required for synchronous flash memories, but can be provided to terminate a read in a manner similar to the SDRAM PRECHARGE command. The ACTIVE TERMINATE command can be issued to terminate a BURST READ in progress, and may or may not be bank specific.

A BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ command prior to the BURST TERMINATE command will be truncated. BURST TERMINATE is not bank specific. The Load Command Register operation is used to initiate flash memory control commands to the Command Execution Logic (CEL) 130. The CEL receives and interprets commands to the device. These commands control the operation of the Internal State Machine 132 and the read path (i.e., memory array 102, ID Register 136 or Status Register 134).

Before any READ or WRITE commands can be issued to a bank within the synchronous flash memory, a row in that bank must be "opened." This is accomplished via the ACTIVE command (defined by CS#, WE#, RAS#, CAS#), which selects both the bank and the row to be activated, see Figure 4.

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to a time period ( tRCD) specification, tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 30ns with a 90 MHZ clock (11.1 Ins period) results in 2.7 clocks, which is rounded to 3. This is reflected in Figure 5, which covers any case where 2 < tRCD (MIN)/tCK <_3. (The same procedure is used to convert other specification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can be issued without having to close a previous active row, provided the minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTINE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by a time period tRRD.

READ bursts are initiated with a READ command (defined by CS#, WE#, RAS#, CAS#), as shown in Figure 6. The starting column and bank addresses are provided with the READ command. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data- out element will be valid by the next positive clock edge. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go to a High-Z state. A full page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.) Data from any READ burst may be truncated with a subsequent READ command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two and three; data element n + 3 is either the last of a burst of four, or the last desired of a longer burst. The synchronous flash memory uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8, or each subsequent READ may be performed to a different bank.

Data from any READ burst may be truncated with a subsequent WRITE command (WRITE commands must be preceded by WRITE SETUP), and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be the possibility that the device driving the input data would go Low-Z before the synchronous flash memory DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention as shown in Figure 9. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal. The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle.

A fixed-length or full-page READ burst can be truncated with either ACTINE TERMINATE (may or may not be bank specific) or BURST TERMINATE (not bank specific) commands. The ACTINE TERMINATE or BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 10 for each possible CAS latency; data element 72 + 3 is the last desired data element of a burst of four or the last desired of a longer burst.

A single-location WRITE is initiated with a WRITE command (defined by CS#, WE#, RAS#, CAS#) as shown in Figure 11. The starting column and bank addresses are provided with the WRITE command. Once a WRITE command is registered, a READ command can be executed as defined by Truth Tables 4 and 5. An example is shown in Figure 12. During a WRITE, the valid data-in is registered coincident with the WRITE command.

Unlike SDRAM, synchronous flash does not require a PRECHARGE command to deactivate the open row in a particular bank or the open rows in all banks. The ACTINE

TERMINATE command is similar to the BURST TERMINATE command; however, ACTIVE TERMINATE may or may not be bank specific. Asserting input A10 HIGH during an ACTINE TERMINATE command will terminate a BURST READ in any bank. When A10 is low during an ACTIVE TERMINATE command, BAO and BAl will determine which bank will undergo a terminate operation. ACTIVE TERMINATE is considered a NOP for banks not addressed by A10, BA0, BA1.

Power-down occurs if clock enable, CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no accesses are in progress. Entering power-down deactivates the input and output buffers (excluding CKE) after internal state machine operations (including WRITE operations) are completed, for power savings while in standby.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting'tCKS). See Figure 13 for an example power-down operation.

A clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, an internal clock is deactivated, "freezing" the synchronous logic. For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge are ignored, any data present on the DQ pins will remain driven, and burst counters are not incremented, as long as the clock is suspended (see example in Figure 14). Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.

The burst read/single write mode is a default mode in one embodiment. All WRITE commands result in the access of a single column location (burst of one), while READ commands access columns according to the programmed burst length and sequence. The following Truth Table 3 illustrates memory operation using the CKE signal.

TRUTH TABLE 3 - CKE

Figure imgf000020_0001

TRUTH TABLE 4 - Current State Bank n - Command to Bank n

Figure imgf000020_0002

Figure imgf000021_0001

TRUTH TABLE 5 - Current State Bank n - Command to Bank m

Figure imgf000021_0002
Figure imgf000022_0001

FUNCTION DESCRIPTION

The synchronous flash memory incorporates a number of features to make it ideally suited for code storage and execute-in-place applications on an SDRAM bus. The memory array is segmented into individual erase blocks. Each block may be erased without affecting data stored in other blocks. These memory blocks are read, written and erased by issuing commands to the command execution logic 130 (CEL). The CEL controls the operation of the Internal State Machine 132 (ISM), which completely controls all ERASE NVMODE REGISTER, WRITE NVMODE REGISTER, WRITE, BLOCK ERASE, BLOCK PROTECT, DEVICE PROTECT, UNPROTECT ALL BLOCKS and VERIFY operations. The ISM 132 protects each memory location from over-erasure and optimizes each memory location for maximum data retention. In addition, the ISM greatly simplifies the control necessary for writing the device in-system or in an external programmer.

The synchronous flash memory is organized into 16 independently erasable memory blocks that allow portions of the memory to be erased without affecting the rest of the memory data. Any block may be hardware-protected against inadvertent erasure or writes. A protected block requires that the RP# pin be driven to VHH (a relatively high voltage) before being modified. The 256K-word blocks at locations 0 and 15 can have additional hardware protection. Once a PROTECT BLOCK command has been executed to these blocks, an UNPROTECT ALL BLOCKS command will unlock all blocks except the blocks at locations 0 and 15, unless the RP# pin is at VHH. This provides additional security for critical code during in-system firmware updates, should an unintentional power disruption or system reset occur.

Power-up initialization, ERASE, WRITE and PROTECT timings are simplified by using an ISM to control all programming algorithms in the memory array. The ISM ensures protection against over-erasure and optimizes write margin to each cell. During WRITE operations, the ISM automatically increments and monitors WRITE attempts, verifies write margin on each memory cell and updates the ISM Status Register. When a BLOCK ERASE operation is performed, the ISM automatically Overwrites the entire addressed block (eliminates over- erasure), increments and monitors ERASE attempts and sets bits in the ISM Status Register.

The 8-bit ISM Status Register 134 allows an external processor 200 to monitor the status of the ISM during WRITE, ERASE and PROTECT operations. One bit of the 8-bit Status Register (SR7) is set and cleared entirely by the ISM. This bit indicates whether the ISM is busy with an ERASE, WRITE or PROTECT task. Additional error information is set in three other bits (SR3, SR4 and SR5): write and protect block error, erase and unprotect all blocks error, and device protection error. Status register bits SRO, SRI and SR2 provide details on the ISM operation underway. The user can monitor whether a device-level or bank-level ISM operation (including which bank is under ISM control) is underway. These six bits (SR3-SR5) must be cleared by the host system. The Status Register is describe in further detail below with reference to Table 2. The CEL 130 receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, device configuration or Status Register). Commands may be issued to the CEL while the ISM is active. To allow for maximum power conservation, the synchronous flash features a very low current, deep power-down mode. To enter this mode, the RP# pin 140 (reset/power-down) is taken to VSS ±0.2V. To prevent an inadvertent RESET, RP# must be held at Vss for 100ns prior to the device entering the reset mode. With RP# held at Vss, the device will enter the deep power-down mode. After the device enters the deep power-down mode, a transition from LOW to HIGH on RP# will result in a device power-up initialize sequence as outlined herein.

Transitioning RP# from LOW to HIGH after entering the reset mode but prior to entering deep power-down mode requires a lμs delay prior to issuing an executable command. When the device enters the deep power-down mode, all buffers excluding the RP# buffer are disabled and the current draw is low, for example, a maximum of 50μA at 3.3V VCC. The input to RP# must remain at Vss during deep power-down. Entering the RESET mode clears the Status Register 134 and sets the ISM 132 to the array read mode.

The synchronous flash memory array architecture is designed to allow sectors to be erased without disturbing the rest of the array. The array is divided into 16 addressable "blocks" that are independently erasable. By erasing blocks rather than the entire array, the total device endurance is enhanced, as is system flexibility. Only the ERASE and BLOCK PROTECT functions are block oriented. The 16 addressable blocks are equally divided into four banks 104, 106, 108 and 110 of four blocks each. The four banks have simultaneous read- while-write functionality. An ISM WRITE or ERASE operation to any bank can occur simultaneously to a READ operation to any other bank. The Status Register 134 may be polled to determine which bank is under ISM operation. The synchronous flash memory has a single background operation ISM to control power-up initialization, ERASE, WRITE, and PROTECT operations. Only one ISM operation can occur at any time; however, certain other commands, including READ operations, can be performed while the ISM operation is taking place. An operational command controlled by the ISM is defined as either a bank-level operation or a device-level operation. WRITE and ERASE are bank-level ISM operations. After an ISM bank operation has been initiated, a READ to any location in the bank may output invalid data, whereas a READ to any other bank will read the array. A READ STATUS REGISTER command will output the contents of the Status Register 134. The ISM status bit will indicate when the ISM operation is complete (SR7 = 1). When the ISM operation is complete, the bank will automatically enter the array read mode. ERASE NVMODE REGISTER, WRITE NVMODE REGISTER, BLOCK PROTECT, DEVICE PROTECT, and UNPROTECT ALL BLOCKS are device-level ISM operations. Once an ISM device-level operation has been initiated, a READ to any bank will output the contents of the array. A READ STATUS REGISTER command may be issued to determine completion of the ISM operation. When SR7 = 1, the ISM operation will be complete and a subsequent ISM operation may be initiated. Any block may be protected from unintentional ERASE or WRITE with a hardware circuit that requires the RP# pin be driven to VHH before a WRITE or ERASE is commenced, as explained below.

Any block may be hardware-protected to provide extra security for the most sensitive portions of the firmware. During a WRITE or ERASE of a hardware protected block, the RP# pin must be held at VHH until the WRITE or ERASE is completed. Any WRITE or ERASE attempt on a protected block without RP# =VHH will be prevented and will result in a write or erase error. The blocks at locations 0 and 15 can have additional hardware protection to prevent an inadvertent WRITE or ERASE operation. In this embodiment, these blocks cannot be software-unlocked through an UNPROTECT ALL BLOCKS command unless RP# =VHH. The protection status of any block may be checked by reading its block protect bit with a READ STATUS REGISTER command. Further, to protect a block, a three-cycle command sequence must be issued with the block address.

The synchronous flash memory can feature three different types of READs. Depending on the mode, a READ operation will produce data from the memory array, status register, or one of the device configuration registers. A READ to the device configuration register or the Status

Register must be preceded by an LCR- ACTIVE cycle and burst length of data out will be defined by the mode register settings. A subsequent READ or a READ not preceded by an LCR- ACTIVE cycle will read the array. However, several differences exist and are described in the following section. A READ command to any bank outputs the contents of the memory array. While a WRITE or ERASE ISM operation is taking place, a READ to any location in the bank under ISM control may output invalid data. Upon exiting a RESET operation, the device will automatically enter the array read mode.

Performing a READ of the Status Register 134 requires the same input sequencing as when reading the array, except that an LCR READ STATUS REGISTER (70H) cycle must precede the ACTIVE READ cycles. The burst length of the Status Register data-out is defined by the Mode Register 148. The Status Register contents are updated and latched on the next positive clock edge subject to CAS latencies. The device will automatically enter the array read mode for subsequent READs. Reading any of the Device Configuration Registers 136 requires the same input sequencing as when reading the Status Register except that specific addresses must be issued. WE# must be HIGH, and DQM and CS# must be LOW. To read the manufacturer compatibility ID, addresses must be at 000000H, and to read the device ID, addresses must be at 00000 IH. Any of the block protect bits is read at the third address location within each erase block (xx0002H), while the device protect bit is read from location 000003H.

The DQ pins are used either to input data to the array. The address pins are used either to specify an address location or to input a command to the CEL during the LOAD COMMAND REGISTER cycle. A command input issues an 8-bit command to the CEL to control the operation mode of the device. A WRITE is used to input data to the memory array. The following section describes both types of inputs.

To perform a command input, DQM must be LOW, and CS# and WE# must be LOW. Address pins or DQ pins are used to input commands. Address pins not used for input commands are "Don't Care" and must be held stable. The 8-bit command is input on DQ0-DQ7 or A0-A7 and is latched on the positive clock edge. A WRITE to the memory array sets the desired bits to logic 0s but cannot change a given bit to a logic 1 from a logic 0. Setting any bits to a logic 1 requires that the entire block be erased. To perform a WRITE, DQM must be LOW, CS# and WE# must be LOW, and VCCP must be tied to VCC. Writing to a protected block also requires that the RP# pin be brought to VHH. A0-A11 provide the address to be written, while the data to be written to the array is input on the DQ pins. The data and addresses are latched on the rising edge of the clock. A WRITE must be preceded by a WRITE SETUP command.

To simplify the writing of the memory blocks, the synchronous flash incorporates an ISM that controls all internal algorithms for the WRITE and ERASE cycles. An 8-bit command set is used to control the device. See Truth Tables 1 and 2 for a list of the valid commands. The 8-bit ISM Status Register 134 (see Table 2) is polled to check for ERASE NVMODE REGISTER, WRITE NVMODE REGISTER, WRITE, ERASE, BLOCK PROTECT, DEVICE PROTECT or UNPROTECT ALL BLOCKS completion or any related errors. Completion of an ISM operation can be monitored by issuing a READ STATUS REGISTER (70H) command. The contents of the Status Register will be output to DQ0-DQ7 and updated on the next positive clock edge (subject to CAS latencies) for a fixed burst length as defined by the mode register settings. The ISM operation will be complete when SR7 = 1. All of the defined bits are set by the ISM, but only the ISM status bit is reset by the ISM. The erase/unprotect block, write/protect block, device protection must be cleared using a CLEAR STATUS REGISTER (50H) command. This allows the user to choose when to poll and clear the Status Register. For example, a host system may perform multiple WRITE operations before checking the Status Register instead of checking after each individual WRITE. Asserting the RP# signal or powering down the device will also clear the Status Register.

TABLE 2 STATUS REGISTER

Figure imgf000027_0001
Figure imgf000028_0001

The device ID, manufacturer compatibility ID, device protection status and block protect status can all be read by issuing a READ DEVICE CONFIGURATION (90H) command. To read the desired register, a specific address must be asserted. See Table 3 for more details on the various device configuration registers 136.

Table 3 DEVICE CONFIGURATION

Figure imgf000029_0001

Commands can be issued to bring the device into different operational modes. Each mode has specific operations that can be performed while in that mode. Several modes require a sequence of commands to be written before they are reached. The following section describes the properties of each mode, and Truth Tables 1 and 2 list all command sequences required to perform the desired operation. Read- while-write functionality allows a background operation write or erase to be performed on any bank while simultaneously reading any other bank. For a write operation, the LCR- ACTIVE- WRITE command sequences in Truth Table 2 must be completed on consecutive clock cycles. However, to simplify a synchronous flash controller operation, an unlimited number of NOPs or COMMAND INHIBITS can be issued throughout the command sequence. For additional protection, these command sequences must have the same bank address for the three cycles. If the bank address changes during the LCR- ACTIVE- WRITE command sequence, or if the command sequences are not consecutive (other than NOPs and COMMAND INHIBITS, which are permitted), the write and erase status bits (SR4 and SR5) will be set and the operation prohibited.

Upon power-up and prior to issuing any operational commands to the device, the synchronous flash is initialized. After power is applied to VCC, VCCQ and VCCP (simultaneously), and the clock is stable, RP# is transitioned from LOW to HIGH. A delay (in one embodiment a lOOμs delay) is required after RP# transitions HIGH in order to complete internal device initialization. The device is in the array read mode at the completion of device initialization, and an executable command can be issued to the device.

To read the device ID, manufacturer compatibility ID, device protect bit and each of the block protect bits, a READ DEVICE CONFIGURATION (90H) command is issued. While in this mode, specific addresses are issued to read the desired information. The manufacturer compatibility ID is read at 000000H; the device ID is read at 00000 IH. The manufacturer compatibility ID and device ID are output on DQ0-DQ7. The device protect bit is read at 000003H; and each of the block protect bits is read at the third address location within each block (xx0002H). The device and block protect bits are output on DQ0.

Three consecutive commands on consecutive clock edges are needed to input data to the array (NOPs and Command Inhibits are permitted between cycles). In the first cycle, a LOAD COMMAND REGISTER command is given with WRITE SETUP (40H) on A0-A7, and the bank address is issued on BAO, BAl . The next command is ACTIVE, which activates the row address and confirms the bank address. The third cycle is WRITE, during which the starting column, the bank address, and data are issued. The ISM status bit will be set on the following clock edge (subject to CAS latencies). While the ISM executes the WRITE, the ISM status bit (SR7) will be at 0. A READ operation to the bank under ISM control may produce invalid data. When the ISM status bit (SR7) is set to a logic 1, the WRITE has been completed, and the bank will be in the array read mode and ready for an executable command. Writing to hardware- protected blocks also requires that the RP# pin be set to VHH prior to the third cycle (WRITE), and RP# must be held at VHH until the ISM WRITE operation is complete. The write and erase status bits (SR4 and SR5) will be set if the LCR-ACTIVE-WRITE command sequence is not completed on consecutive cycles or the bank address changes for any of the three cycles. After the ISM has initiated the WRITE, it cannot be aborted except by a RESET or by powering down the part. Doing either during a WRITE may corrupt the data being written.

Executing an ERASE sequence will set all bits within a block to logic 1. The command sequence necessary to execute an ERASE is similar to that of a WRITE. To provide added security against accidental block erasure, three consecutive command sequences on consecutive clock edges are required to initiate an ERASE of a block. In the first cycle, LOAD COMMAND REGISTER is given with ERASE SETUP (20H) on A0-A7, and the bank address of the block to be erased is issued on BAO, BAl . The next command is ACTIVE, where A10, Al 1, BAO, BAl provide the address of the block to be erased. The third cycle is WRITE, during which ERASE CONFRJM (DOH) is given on DQ0-DQ7 and the bank address is reissued. The ISM status bit will be set on the following clock edge (subject to CAS latencies). After ERASE CONFIRM (DOH) is issued, the ISM will start the ERASE of the addressed block. Any READ operation to the bank where the addressed block resides may output invalid data. When the ERASE operation is complete, the bank will be in the array read mode and ready for an executable command. Erasing hardware-protected blocks also requires that the RP# pin be set to VHH prior to the third cycle (WRITE), and RP# must be held at VHH until the ERASE is completed (SR7 = 1). If the LCR- ACTIVE- WRITE command sequence is not completed on consecutive cycles (NOPs and COMMAND INHIBITS are permitted between cycles) or the bank address changes for one or more of the command cycles, the write and erase status bits (SR4 and SR5) will be set and the operation is prohibited. The contents of the Mode Register 148 may be copied into the NVMode Register 147 with a WRITE NVMODE REGISTER command. Prior to writing to the NVMode Register, an ERASE NVMODE REGISTER command sequence must be completed to set all bits in the NVMode Register to logic 1. The command sequence necessary to execute an ERASE NVMODE REGISTER and WRITE NVMODE REGISTER is similar to that of a WRITE. See Truth Table 2 for more information on the LCR-ACTIVE-WRITE commands necessary to complete ERASE NVMODE REGISTER and WRITE NVMODE REGISTER. After the WRITE cycle of the ERASE NVMODE REGISTER or WRITE NVMODE REGISTER command sequence has been registered, a READ command may be issued to the array. A new WRITE operation will not be permitted until the current ISM operation is complete and SR7 = 1. Executing a BLOCK PROTECT sequence enables the first level of software/hardware protection for a given block. The memory includes a 16-bit register that has one bit corresponding to the 16 protectable blocks. The memory also has a register to provide a device bit used to protect the entire device from write and erase operations. The command sequence necessary to execute a BLOCK PROTECT is similar to that of a WRITE. To provide added security against accidental block protection, three consecutive command cycles are required to initiate a BLOCK PROTECT. In the first cycle, a LOAD COMMAND REGISTER is issued with a PROTECT SETUP (60H) command on A0-A7, and the bank address of the block to be protected is issued on BAO, BAl. The next command is ACTIVE, which activates a row in the block to be protected and confirms the bank address. The third cycle is WRITE, during which BLOCK PROTECT CONFIRM (01 H) is issued on DQ0- DQ7, and the bank address is reissued. The ISM status bit will be set on the following clock edge (subject to CAS latencies). The ISM will then begin the PROTECT operation. If the LCR-ACTIVE-WRITE is not completed on consecutive cycles (NOPs and COMMAND INHIBITS are permitted between cycles) or the bank address changes, the write and erase status bits (SR4 and SR5) will be set and the operation is prohibited. When the ISM status bit (SR7) is set to a logic 1, the PROTECT has been completed, and the bank will be in the array read mode and ready for an executable command. Once a block protect bit has been set to a 1 (protected), it can only be reset to a 0 if the UNPROTECT ALL BLOCKS command. The UNPROTECT ALL BLOCKS command sequence is similar to the BLOCK PROTECT command; however, in the third cycle, a WRITE is issued with a UNPROTECT ALL BLOCKS CONFIRM (DOH) command and addresses are "Don't Care." For additional information, refer to Truth Table 2. The blocks at locations 0 and 15 have additional security. Once the block protect bits at locations 0 and 15 have been set to a 1 (protected), each bit can only be reset to a 0 if RP# is brought to VHH prior to the third cycle of the UNPROTECT operation, and held at VHH until the operation is complete (SR7 = 1). Further, if the device protect bit is set, RP# must be brought to VHH prior to the third cycle and held at VHH until the BLOCK PROTECT or UNPROTECT ALL BLOCKS operation is complete. To check a block's protect status, a READ DEVICE CON FIGURATION (90H) command may be issued.

Executing a DEVICE PROTECT sequence sets the device protect bit to a 1 and prevents a block protect bit modification. The command sequence necessary to execute a DEVICE PROTECT is similar to that of a WRITE. Three consecutive command cycles are required to initiate a DEVICE PROTECT sequence. In the first cycle, LOAD COMMAND REGISTER is issued with a PROTECT SETUP (60H) on AO- A7, and a bank address is issued on BAO, BAl. The bank address is "Don't Care" but the same bank address must be used for all three cycles. The next command is ACTIVE. The third cycle is WRITE, during which a DEVICE PROTECT (F1H) command is issued on DQ0-DQ7, and RP# is brought to VHH. The ISM status bit will be set on the following clock edge (subject to CAS latencies). An executable command can be issued to the device. RP# must be held at VHH until the WRITE is completed (SR7 = 1). A new WRITE operation will not be permitted until the current ISM operation is complete. Once the device protect bit is set, it cannot be reset to a 0. With the device protect bit set to a 1 j BLOCK PROTECT or BLOCK UNPROTECT is prevented unless RP# is at VHH during either operation. The device protect bit does not affect WRITE or ERASE operations. Refer to Table 4 for more information on block and device protect operations.

Table 4 PROTECT OPERATIONS TRUTH TABLE

Figure imgf000033_0001
After the ISM status bit (SR7) has been set, the device/ bank (SRO), device protect (SR3), bankAO (SRI), bankNl (SR2), write/protect block (SR4) and erase/unprotect (SR5) status bits may be checked. If one or a combination of SR3, SR4, SR5 status bits has been set, an error has occurred during operation. The ISM cannot reset the SR3, SR4 or SR5 bits. To clear these bits, a CLEAR STATUS REGISTER (50H) command must be given. Table 5 lists the combinations of errors.

Table 5 STATUS REGISTER ERROR DECODE

Figure imgf000034_0001

The synchronous flash memory is designed and fabricated to meet advanced code and data storage requirements. To ensure this level of reliability, VCCP must be tied to Vcc during WRITE or ERASE cycles. Operation outside these limits may reduce the number of WRITE and ERASE cycles that can be performed on the device. Each block is designed and processed for a minimum of 100,000-WRITE/ERASE-cycle endurance.

The synchronous flash memory offers several power-saving features that may be utilized in the array read mode to conserve power. A deep power-down mode is enabled by bringing RP# to VSS ±0.2V. Current draw (ICC) in this mode is low, such as a maximum of 50μA. When CS# is HIGH, the device will enter the active standby mode. In this mode the current is also low, such as a maximum ICC current of 30mA. If CS# is brought HIGH during a write, erase, or protect operation, the ISM will continue the WRITE operation, and the device will consume active Iccp power until the operation is completed. Referring to Figure 16, a flow chart of a self-timed write sequence according to one embodiment of the present invention is described. The sequence includes loading the command register (code 40H), receiving an active command and a row address, and receiving a write command and a column address. The sequence then provides for a status register polling to determine if the write is complete. The polling monitors status register bit 7 (SR7) to determine if it is set to a 1. An optional status check can be included. When the write is completed, the array is placed in the array read mode.

Referring to Figure 17, a flow chart of a complete write status-check sequence according to one embodiment of the present invention is provided. The sequence looks for status register bit 4 (SR4) to determine if it is set to a 0. If SR4 is a 1, there was an error in the write operation. The sequence also looks for status register bit 3 (SR3) to determine if it is set to a O. If SR3 is a 1, there was an invalid write error during the write operation.

Referring to Figure 18, a flow chart of a self-timed block erase sequence according to one embodiment of the present invention is provided. The sequence includes loading the command register (code 20H), and receiving an active command and a row address. The memory then determines if the block is protected. If it is not protected, the memory performs a write operation (DOH) to the block and monitors the status register for completion. An optional status check can be performed and the memory is placed in an array read mode. If the block is protected, the erase is not allowed unless the RP# signal is at an elevated voltage (VHH).

Figure 19 illustrates a flow chart of a complete block erase status-check sequence according to one embodiment of the present invention. The sequence monitors the status register to determine if a command sequence error occurred (SR4 or SR5 = 1). If SR3 is set to a 1, an invalid erase or unprotect error occurred. Finally, a block erase or unprotect error happened if SR5 is set to a 1.

Figure 20 is a flow chart of a block protect sequence according to one embodiment of the present invention. The sequence includes loading the command register (code 60H), and receiving an active command and a row address. The memory then determines if the block is protected. If it is not protected, the memory performs a write operation (01H) to the block and monitors the status register for completion. An optional status check can be performed and the memory is placed in an array read mode. If the block is protected, the erase is not allowed unless the RP# signal is at an elevated voltage (VHH).

Referring to Figure 21, a flow chart of a complete block status-check sequence according to one embodiment of the present invention is provided. The sequence monitors the status register bits 3, 4 and 5 to determine of errors were detected.

Figure 22 is a flow chart of a device protect sequence according to one embodiment of the present invention. The sequence includes loading the command register (code 60H), and receiving an active command and a row address. The memory then determines if RP# is at VHH. The memory performs a write operation (F1H) and monitors the status register for completion. An optional status check can be performed and the memory is placed in an array read mode. Figure 23 is a flow chart of a block unprotect sequence according to one embodiment of the present invention. The sequence includes loading the command register (code 60H), and receiving an active command and a row address. The memory then determines if the memory device is protected. If it is not protected, the memory determines if the boot locations (blocks 0 and 15 ) are protected. If none of the blocks are protected the memory performs a write operation (DOH) to the block and monitors the status register for completion. An optional status check can be performed and the memory is placed in an array read mode. If the device is protected, the erase is not allowed unless the RP# signal is at an elevated voltage (VHH). Likewise, if the boot locations are protected, the memory determines if all blocks should be unprotected.

Figure 24 illustrates the timing of an initialize and load mode register operation. The mode register is programmed by providing a load mode register command and providing operation code (opcode) on the address lines. The opcode is loaded into the mode register. As explained above, the contents of the non-volatile mode register are automatically loaded into the mode register upon power-up and the load mode register operation may not be needed.

Figure 25 illustrates the timing of a clock suspend mode operation, and Figure 26 illustrates the timing of another burst read operation. Figure 27 illustrates the timing of alternating bank read accesses. Here active command are needed to change bank addresses. A full page burst read operation is illustrated in Figure 28. Note that the full page burst does not self terminate, but requires a terminate command.

Figure 29 illustrates the timing of a read operation using a data mask signal. The DQM signal is used to mask the data output so that Dout m+1 is not provided on the DQ connections. Referring to Figure 30, the timing of a write operation followed by a read to a different bank is illustrated. In this operation, a write is performed to bank a and a subsequent read is performed to bank b. The same row is accessed in each bank.

Referring to Figure 31 , the timing of a write operation followed by a read to the same bank is illustrated. In this operation, a write is performed to bank a and a subsequent read is performed to bank a. A different row is accessed for the read operation, and the memory must wait for the prior write operation to be completed. This is different from the read of Figure 30 where the read was not delayed due to the write operation.

Consistent latency for all read operations. The synchronous flash of the present invention is designed to read the memory in the same basic manner as an SDRAM. The synchronous Flash memory, therefore, has a read latency. In prior Flash memories, other read operations such as reading a status register 282 or intelligent identifier registers could be performed. These registers read data placed in the register 282 using a multiplex circuit 280 that directed the data traffic depending on the mode of operation, see Figure 32 for an illustration of a prior art system. Here the data of the status register 282 is output from the multiplex circuit 280. A second input of the multiplex circuit is coupled to receive data from a pipeline buffer 284 and memory array read circuitry 286. An output data buffer circuit 288 is coupled to output data from the multiplex circuit to the DQ connections. This prior system can result in problems with the present synchronous flash. Depending on which mode the chip is operating under (array read or register read), the data read latencies would be different. This could introduce problems for the bus controller when reading data from the registers and would most likely create bus contention. That is, outputting data from a multiplex circuit may provide data that does not have a read latency that matches a latency of the memory data reads. The present invention has a different output design. Referring to Figure 33, the present flash memory includes a multiplex circuit 302 coupled to the input of a pipeline buffer 304. In one embodiment the output buffer has three pipeline paths that can be selected to provide one, two or three clock latency during read operations. The memory array read circuitry 124, status register 134 and the identification (configuration) register 136 are coupled to the multiplex circuit 302. The multiplex circuit is coupled to the pipeline circuit and the output buffer circuit 306. Thus, both the memory array data and the register data are processed through the pipeline path selected. This insures that the data from the registers has the same clock latency as the array data. Bus contention due to register read operations, therefore, is reduced with the present invention.

Conclusion

A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device includes a pipelined buffer with selectable propagation paths to route data from the input connection to the output connection. Each propagation path requires a predetermined number of clock cycles. The non- volatile synchronous memory includes circuitry to route both memory data and register data through the pipelined output buffer to maintain consistent latency for both types of data. In one embodiment, the circuitry includes a multiplex circuit coupled to the input of the pipeline buffer. A data register circuit is coupled to a first input of the multiplex circuit, and a data read circuit is coupled to a second input of the multiplex circuit. The data read circuit provides output data read from a memory array of the synchronous memory device.

Claims

What is claimed is:
1. A synchronous memory device comprising: a pipeline buffer having an input connection and an output connection, the pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles; a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a first and second input; a data register circuit coupled to the first input of the multiplex circuit; and a data read circuit coupled to the second input of the multiplex circuit, the data read circuit provides output data read from a memory array of the synchronous memory device.
2. The synchronous memory device of claim 1 wherein the pipeline buffer has three propagation paths that can be selected to provide one, two or three clock latency during read operations.
3. The synchronous memory device of claim 1 wherein the data register circuit comprises a status register to provide status data.
4. The synchronous memory device of claim 3 wherein the status data comprises an active status of a state machine of the synchronous memory device; a memory array bank status; and operation error data.
5. The synchronous memory device of claim 1 wherein the array of memory cells comprises an array of non-volatile memory cells.
6. A synchronous flash memory device comprising: an array of non- volatile memory cells; a pipeline buffer having an input connection and an output connection, the pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the output connection wherein each propagation path requires a predetermined number of clock cycles; a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a first and second input; a data register circuit coupled to the first input of the multiplex circuit; and a data read circuit coupled to the second input of the multiplex circuit, the data read circuit provides output data read from the array of non- volatile memory cells, such that data from the data register circuit and the data read circuit propagate through the pipeline buffer circuit using one of the plurality of selectable propagation paths.
7. The synchronous memory device of claim 6 wherein the pipeline buffer has three propagation paths that can be selected to provide one, two or three clock latency during read operations.
8. A processing system comprising: a memory controller; and a synchronous flash memory device coupled to the memory controller and comprising: an array of non- volatile memory cells, a pipeline buffer having an input connection and a data output connection, the pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the data output connection wherein each propagation path requires a predetermined number of clock cycles, the data output connection is coupled to the memory controller via a data bus, a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a first and second input, a status register circuit coupled to the first input of the multiplex circuit, and a memory read circuit coupled to the second input of the multiplex circuit, the data read circuit provides data read from the array of non-volatile memory cells, such that data from the status register circuit and the memory read circuit propagate through the pipeline buffer circuit using one of the plurality of selectable propagation paths.
9. The processing system of claim 8 wherein the plurality of selectable propagation paths comprise one, two and three clock cycle propagation delays.
10. A processing system comprising: a memory controller; and a synchronous flash memory device coupled to the memory controller, wherein the memory controller receives memory cell data from the synchronous flash memory device a first predetermined number of clock cycles after a memory column address has been provided by the memory controller, and the memory controller receives status data from the synchronous flash memory device a second predetermined number of clock cycles after a status read request has been provided by the memory controller, the first and second predetermined number of clock cycles are equal.
11. The processing system of claim 10 wherein the synchronous flash memory device comprises: an array of non-volatile memory cells, a pipeline buffer having an input connection and a data output connection, the pipeline buffer has a plurality of selectable propagation paths to route data from the input connection to the data output connection wherein each propagation path requires a predetermined number of clock cycles, the data output connection is coupled to the memory controller via a data bus, a multiplex circuit coupled to the input of the pipeline buffer, the multiplex circuit having a first and second input, a status register circuit coupled to the first input of the multiplex circuit, and a memory read circuit coupled to the first input of the multiplex circuit, the data read circuit provides data read from the array of non-volatile memory cells, such that data from the status register circuit and the memory read circuit propagate through the pipeline buffer circuit using one of the plurality of selectable propagation paths.
12. The processing system of claim 10 wherein the first and second predetermined number of clock cycles comprises one, two and three clock cycles.
13. A synchronous flash memory device comprising: an array of non- volatile memory cells; and a pipeline buffer coupled to an external data connection to provide memory read data in response to a read request and provide status register data in response to a status request, wherein the synchronous flash memory device provides the memory read data on the external data connection a predetermined number of clock cycles following the read request, and the synchronous flash memory device provides the status register data on the external data connection the predeteπnined number of clock cycles following the status request, such that the memory read data and the status register data have a same clock latency.
14. The synchronous flash memory device of claim 13 further comprising: a multiplex circuit coupled to an input of the pipeline buffer, the multiplex circuit having a first and second input; a status register coupled to the first input of the multiplex circuit; and an aπay read circuit coupled to the first input of the multiplex circuit, the data read circuit provides the memory read data from a memory aπay.
15. The synchronous flash memory device of claim 13 wherein the predetermined number of clock cycles is either one, two or three clock cycles.
16. A method of reading from a synchronous flash memory device, the method comprising: initiating a memory cell read operation; outputting memory cell data in response to the memory cell read operation, the memory cell data is output on data connections a predetermined number of clock cycles after the memory cell read operation is initiated; initiating a status read operation; outputting status data in response to the status read operation, the status data is output on the data connections the predetermined number of clock cycles after the status read operation is initiated.
17. The method of claim 16 wherein outputting the memory cell data comprises coupling the memory cell data to an input of a pipeline buffer and propagating the memory cell data through the pipeline buffer during the predetermined number of clock cycles.
18. The method of claim 16 wherein outputting the status data comprises coupling the status data to an input of a pipeline buffer and propagating the status data through the pipeline buffer during the predetermined number of clock cycles.
19. The method of claim 16 wherein outputting memory cell data comprises coupling the memory cell data to an input of a pipeline buffer and propagating the memory cell data through the pipeline buffer during the predeteπnined number of clock cycles, and wherein outputtmg the status data comprises coupling the status data to the input of the pipeline buffer and propagating the status data through the pipeline buffer during the predetermined number of clock cycles
20. The method of claim 19 wherein the memory cell data and the status data are selectively coupled to the pipeline buffer using a multiplex circuit.
21. The method of claim 16 wherein the predetermined number of clock cycles is either one, two or three clock cycles.
22. A method of reading data from a synchronous memory device, the method comprising: coupling either memory cell data or status data to an input connection of a pipeline buffer; propagating the memory cell data or the status data through the pipeline buffer; and outputting either the memory cell data or the status data on external data connections.
23. The method of claim 22 wherein coupling either the memory cell data or the status data comprises: reading the memory cell data and coupling the memory cell data to a first input of a multiplex circuit; reading the status data and coupling the status data to a second input of the multiplex circuit; and selectively coupling either the first or second input to the pipeline buffer through the multiplex circuit.
24. The method of claim 22 wherein the pipeline buffer has a plurality of selectable propagation paths.
25. The method of claim 24 wherein the plurality of selectable propagation paths have a time delay of one, two or three clock cycles.
26. A method of reading data from a synchronous memory device, the method comprising: reading memory cell data and coupling the memory cell data to a first input of a multiplex circuit; reading status data from a status register and coupling the status data to a second input of the multiplex circuit; selectively coupling either the first or second input to an input of a pipeline buffer through the multiplex circuit, wherein the pipeline buffer has a plurality of selectable propagation paths; propagating the memory cell data or the status data through the pipeline buffer; and outputting either the memory cell data or the status data on external data connections.
27. The method of claim 26 wherein the plurality of selectable propagation paths have a time delay of either one, two or three clock cycles.
PCT/US2001/010040 2000-03-30 2001-03-30 Flash with consistent latency for read operations WO2001075896A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US19350600P true 2000-03-30 2000-03-30
US60/193,506 2000-03-30
US09/567,733 2000-05-10
US09/567,733 US6615307B1 (en) 2000-05-10 2000-05-10 Flash with consistent latency for read operations

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE10196011T DE10196011B3 (en) 2000-03-30 2001-03-30 Synchronous memory device and method for reading data from a synchronous memory device
KR20027013097A KR100508042B1 (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations
AU8929101A AU8929101A (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations
JP2001573488A JP3631209B2 (en) 2000-03-30 2001-03-30 Flash with consistent latency in read processing

Publications (3)

Publication Number Publication Date
WO2001075896A2 true WO2001075896A2 (en) 2001-10-11
WO2001075896A3 WO2001075896A3 (en) 2002-02-28
WO2001075896A9 WO2001075896A9 (en) 2002-12-19

Family

ID=26889061

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2001/010040 WO2001075896A2 (en) 2000-03-30 2001-03-30 Flash with consistent latency for read operations

Country Status (5)

Country Link
JP (1) JP3631209B2 (en)
KR (1) KR100508042B1 (en)
AU (1) AU8929101A (en)
DE (1) DE10196011B3 (en)
WO (1) WO2001075896A2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6877080B2 (en) * 2000-05-10 2005-04-05 Micron Technology, Inc. Flash with consistent latency for read operations
CN105593942A (en) * 2013-09-30 2016-05-18 美光科技公司 Volatile memory architecture in non-volatile memory devices and related controllers

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100618696B1 (en) * 2004-04-28 2006-09-08 주식회사 하이닉스반도체 Memory device including self-ID number
KR100762259B1 (en) 2005-09-12 2007-10-01 삼성전자주식회사 Nand flash memory device with burst read latency function
JP5266589B2 (en) * 2009-05-14 2013-08-21 ルネサスエレクトロニクス株式会社 Nonvolatile semiconductor memory device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
US5978311A (en) * 1998-03-03 1999-11-02 Micron Technology, Inc. Memory with combined synchronous burst and bus efficient functionality
EP0978842A1 (en) * 1998-08-04 2000-02-09 Samsung Electronics Co., Ltd. Synchronous burst semiconductor memory device
US6044023A (en) * 1995-02-10 2000-03-28 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5889726A (en) * 1997-11-17 1999-03-30 Micron Electronics, Inc. Apparatus for providing additional latency for synchronously accessed memory

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6044023A (en) * 1995-02-10 2000-03-28 Townsend And Townsend And Crew Llp Method and apparatus for pipelining data in an integrated circuit
US5917761A (en) * 1997-11-06 1999-06-29 Motorola Inc. Synchronous memory interface
US5978311A (en) * 1998-03-03 1999-11-02 Micron Technology, Inc. Memory with combined synchronous burst and bus efficient functionality
EP0978842A1 (en) * 1998-08-04 2000-02-09 Samsung Electronics Co., Ltd. Synchronous burst semiconductor memory device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6877080B2 (en) * 2000-05-10 2005-04-05 Micron Technology, Inc. Flash with consistent latency for read operations
CN105593942A (en) * 2013-09-30 2016-05-18 美光科技公司 Volatile memory architecture in non-volatile memory devices and related controllers
EP3053168A1 (en) * 2013-09-30 2016-08-10 Micron Technology, INC. Volatile memory architecture in non-volatile memory devices and related controllers
EP3053168A4 (en) * 2013-09-30 2017-05-03 Micron Technology, INC. Volatile memory architecture in non-volatile memory devices and related controllers
KR20180037320A (en) * 2013-09-30 2018-04-11 마이크론 테크놀로지, 인크. Volatile memory architecture in non-volatile memory devices and related controllers
TWI625731B (en) * 2013-09-30 2018-06-01 美商美光科技公司 Volatile memory architecture in non-volatile memory devices and related controllers
KR101940963B1 (en) 2013-09-30 2019-01-21 마이크론 테크놀로지, 인크. Volatile memory architecture in non-volatile memory devices and related controllers

Also Published As

Publication number Publication date
AU8929101A (en) 2001-10-15
WO2001075896A9 (en) 2002-12-19
JP3631209B2 (en) 2005-03-23
KR100508042B1 (en) 2005-08-17
DE10196011B3 (en) 2012-07-26
DE10196011T0 (en)
JP2003529883A (en) 2003-10-07
KR20030014380A (en) 2003-02-17
DE10196011T1 (en) 2003-03-13
WO2001075896A3 (en) 2002-02-28

Similar Documents

Publication Publication Date Title
US10460775B2 (en) Asynchronous/synchronous interface
US9548088B2 (en) Semiconductor memory asynchronous pipeline
JP5588536B2 (en) Memory device, system having memory device, and method of operating embedded device
US8213244B2 (en) Distributed write data drivers for burst access memories
KR100260683B1 (en) Cache sdram device
US7907469B2 (en) Multi-port memory device for buffering between hosts and non-volatile memory devices
JP3843145B2 (en) Synchronous semiconductor memory device
EP0978842B1 (en) Synchronous burst semiconductor memory device
JP4290374B2 (en) Nonvolatile semiconductor memory device having selective double speed operation mode
US6795899B2 (en) Memory system with burst length shorter than prefetch length
US8775719B2 (en) NAND-based hybrid NVM design that integrates NAND and NOR in 1-die with parallel interface
JP4141520B2 (en) Synchronous semiconductor memory device
JP4744765B2 (en) Simultaneous operation of multiple banks of flash memory
KR100284986B1 (en) Distributed write data driver for burst access memory
KR100395732B1 (en) Semiconductor storage device
US6272608B1 (en) Method and apparatus for synchronous data transfers in a memory device with lookahead logic for detecting latency intervals
US5822251A (en) Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers
US7075857B2 (en) Distributed write data drivers for burst access memories
US5684752A (en) Pipelined read architecture for memory
US5587961A (en) Synchronous memory allowing early read command in write to read transitions
US6381180B1 (en) Distributed write data drivers for burst access memories
US8291126B2 (en) Variable read latency on a serial memory bus
KR100257430B1 (en) Cached synchronous dram architecture allowing concurrent dram operations
US7707354B2 (en) SRAM cache and flash micro-controller with differential packet interface
ES2395570T3 (en) Daisy Chain Cascade Device

Legal Events

Date Code Title Description
AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: A2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

ENP Entry into the national phase in:

Ref country code: JP

Ref document number: 2001 573488

Kind code of ref document: A

Format of ref document f/p: F

WWE Wipo information: entry into national phase

Ref document number: 1020027013097

Country of ref document: KR

COP Corrected version of pamphlet

Free format text: PAGES 1/33-33/33, DRAWINGS, REPLACED BY NEW PAGES 1/36-36/36; DUE TO LATE TRANSMITTAL BY THE RECEIVING OFFICE

AL Designated countries for regional patents

Kind code of ref document: C2

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

AK Designated states

Kind code of ref document: C2

Designated state(s): AE AG AL AM AT AU AZ BA BB BG BR BY BZ CA CH CN CO CR CU CZ DE DK DM DZ EE ES FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

WWP Wipo information: published in national office

Ref document number: 1020027013097

Country of ref document: KR

122 Ep: pct application non-entry in european phase
WWG Wipo information: grant in national office

Ref document number: 1020027013097

Country of ref document: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8607