DE60128679D1 - Nachschlagtabelle für nutzerprogrammierbares gatterfeld mit zwei toren für schreiblese- und schieberegister- modus - Google Patents

Nachschlagtabelle für nutzerprogrammierbares gatterfeld mit zwei toren für schreiblese- und schieberegister- modus

Info

Publication number
DE60128679D1
DE60128679D1 DE60128679T DE60128679T DE60128679D1 DE 60128679 D1 DE60128679 D1 DE 60128679D1 DE 60128679 T DE60128679 T DE 60128679T DE 60128679 T DE60128679 T DE 60128679T DE 60128679 D1 DE60128679 D1 DE 60128679D1
Authority
DE
Germany
Prior art keywords
gatterfield
gates
writing
shift register
reference table
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60128679T
Other languages
English (en)
Other versions
DE60128679T2 (de
Inventor
Trevor J Bauer
Steven P Young
Richard A Carberry
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xilinx Inc
Original Assignee
Xilinx Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xilinx Inc filed Critical Xilinx Inc
Application granted granted Critical
Publication of DE60128679D1 publication Critical patent/DE60128679D1/de
Publication of DE60128679T2 publication Critical patent/DE60128679T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724—Structural details of logic blocks
    • H03K19/17728—Reconfigurable logic blocks, e.g. lookup tables

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE60128679T 2000-05-05 2001-04-06 Nachschlagtabelle für nutzerprogrammierbares gatterfeld mit zwei toren für schreiblese- und schieberegister- modus Expired - Lifetime DE60128679T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US565431 2000-05-05
US09/565,431 US6373279B1 (en) 2000-05-05 2000-05-05 FPGA lookup table with dual ended writes for ram and shift register modes
PCT/US2001/011425 WO2001086813A2 (en) 2000-05-05 2001-04-06 Fpga lookup table with dual ended writes for ram and shift register modes

Publications (2)

Publication Number Publication Date
DE60128679D1 true DE60128679D1 (de) 2007-07-12
DE60128679T2 DE60128679T2 (de) 2008-01-24

Family

ID=24258562

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60128679T Expired - Lifetime DE60128679T2 (de) 2000-05-05 2001-04-06 Nachschlagtabelle für nutzerprogrammierbares gatterfeld mit zwei toren für schreiblese- und schieberegister- modus

Country Status (5)

Country Link
US (1) US6373279B1 (de)
EP (1) EP1279228B1 (de)
CA (1) CA2411486C (de)
DE (1) DE60128679T2 (de)
WO (1) WO2001086813A2 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6667635B1 (en) 2002-09-10 2003-12-23 Xilinx, Inc. FPGA lookup table with transmission gate structure for reliable low-voltage operation
US6914450B2 (en) * 2003-11-06 2005-07-05 International Business Machines Corporation Register-file bit-read method and apparatus
DE102004006769B3 (de) * 2004-02-11 2005-08-11 Infineon Technologies Ag Auslesevorrichtung
US7463602B2 (en) * 2004-09-13 2008-12-09 Research In Motion Limited Configuring signaling radio bearer information in a user equipment protocol stack
US7375552B1 (en) 2005-06-14 2008-05-20 Xilinx, Inc. Programmable logic block with dedicated and selectable lookup table outputs coupled to general interconnect structure
US7215138B1 (en) 2005-06-14 2007-05-08 Xilinx, Inc. Programmable lookup table with dual input and output terminals in shift register mode
US7205790B1 (en) 2005-06-14 2007-04-17 Xilinx, Inc. Programmable integrated circuit providing efficient implementations of wide logic functions
US7218139B1 (en) 2005-06-14 2007-05-15 Xilinx, Inc. Programmable integrated circuit providing efficient implementations of arithmetic functions
US7193433B1 (en) 2005-06-14 2007-03-20 Xilinx, Inc. Programmable logic block having lookup table with partial output signal driving carry multiplexer
US7265576B1 (en) 2005-06-14 2007-09-04 Xilinx, Inc. Programmable lookup table with dual input and output terminals in RAM mode
US7233168B1 (en) 2005-06-14 2007-06-19 Xilinx, Inc. Methods of setting and resetting lookup table memory cells
US7804719B1 (en) 2005-06-14 2010-09-28 Xilinx, Inc. Programmable logic block having reduced output delay during RAM write processes when programmed to function in RAM mode
US7202697B1 (en) 2005-06-14 2007-04-10 Xilinx, Inc. Programmable logic block having improved performance when functioning in shift register mode
US20070138644A1 (en) * 2005-12-15 2007-06-21 Tessera, Inc. Structure and method of making capped chip having discrete article assembled into vertical interconnect
US7420390B1 (en) * 2006-01-09 2008-09-02 Altera Corporation Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size
CN101179277B (zh) * 2006-11-06 2010-06-16 盛群半导体股份有限公司 高延伸性的译码电路及译码方法
US20080180133A1 (en) * 2007-01-29 2008-07-31 Wen-Chi Hsu Expandable decoding circuit and decoding method
US7948791B1 (en) 2009-01-15 2011-05-24 Xilinx, Inc. Memory array and method of implementing a memory array
US8369120B2 (en) * 2010-03-19 2013-02-05 Qualcomm Incorporated Methods and apparatus for sum of address compare write recode and compare reduction
TWI459394B (zh) * 2011-01-03 2014-11-01 Etron Technology Inc 產生記憶體晶片的測試樣式的裝置及其方法
US9940995B1 (en) 2017-01-31 2018-04-10 Intel Corporation Methods and apparatus for reusing lookup table random-access memory (LUTRAM) elements as configuration random-access memory (CRAM) elements
US10566050B1 (en) 2018-03-21 2020-02-18 Xilinx, Inc. Selectively disconnecting a memory cell from a power supply
CN109815545B (zh) * 2018-12-25 2023-04-07 河南工程学院 基于寄存器重定时的多流水级时序电路再综合操作方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4750155A (en) 1985-09-19 1988-06-07 Xilinx, Incorporated 5-Transistor memory cell which can be reliably read and written
US5566123A (en) * 1995-02-10 1996-10-15 Xilinx, Inc. Synchronous dual port ram
US5821773A (en) * 1995-09-06 1998-10-13 Altera Corporation Look-up table based logic element with complete permutability of the inputs to the secondary signals
US6020758A (en) * 1996-03-11 2000-02-01 Altera Corporation Partially reconfigurable programmable logic device
US5889413A (en) 1996-11-22 1999-03-30 Xilinx, Inc. Lookup tables which double as shift registers
US5914616A (en) 1997-02-26 1999-06-22 Xilinx, Inc. FPGA repeatable interconnect structure with hierarchical interconnect lines
US5933369A (en) 1997-02-28 1999-08-03 Xilinx, Inc. RAM with synchronous write port using dynamic latches
US5764564A (en) 1997-03-11 1998-06-09 Xilinx, Inc. Write-assisted memory cell and method of operating same
US5995988A (en) * 1997-12-04 1999-11-30 Xilinx, Inc. Configurable parallel and bit serial load apparatus
US6150838A (en) * 1999-02-25 2000-11-21 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit

Also Published As

Publication number Publication date
EP1279228A2 (de) 2003-01-29
DE60128679T2 (de) 2008-01-24
US6373279B1 (en) 2002-04-16
CA2411486C (en) 2010-06-22
WO2001086813A3 (en) 2002-06-27
WO2001086813A2 (en) 2001-11-15
EP1279228B1 (de) 2007-05-30
CA2411486A1 (en) 2001-11-15

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