DE60117735D1 - Pufferspeichersystem - Google Patents

Pufferspeichersystem

Info

Publication number
DE60117735D1
DE60117735D1 DE60117735T DE60117735T DE60117735D1 DE 60117735 D1 DE60117735 D1 DE 60117735D1 DE 60117735 T DE60117735 T DE 60117735T DE 60117735 T DE60117735 T DE 60117735T DE 60117735 D1 DE60117735 D1 DE 60117735D1
Authority
DE
Germany
Prior art keywords
buffer system
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60117735T
Other languages
English (en)
Other versions
DE60117735T2 (de
Inventor
Fumihiko Hayakawa
Hiroshi Okano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of DE60117735D1 publication Critical patent/DE60117735D1/de
Application granted granted Critical
Publication of DE60117735T2 publication Critical patent/DE60117735T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/50—Control mechanisms for virtual memory, cache or TLB
    • G06F2212/502—Control mechanisms for virtual memory, cache or TLB using adaptive policy
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/601—Reconfiguration of cache memory
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE60117735T 2001-02-13 2001-12-20 Pufferspeichersystem Expired - Fee Related DE60117735T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2001035175 2001-02-13
JP2001035175A JP2002236616A (ja) 2001-02-13 2001-02-13 キャッシュメモリシステム

Publications (2)

Publication Number Publication Date
DE60117735D1 true DE60117735D1 (de) 2006-05-04
DE60117735T2 DE60117735T2 (de) 2006-08-17

Family

ID=18898654

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60117735T Expired - Fee Related DE60117735T2 (de) 2001-02-13 2001-12-20 Pufferspeichersystem

Country Status (5)

Country Link
US (1) US20020112126A1 (de)
EP (1) EP1231539B1 (de)
JP (1) JP2002236616A (de)
KR (1) KR100794973B1 (de)
DE (1) DE60117735T2 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100395756B1 (ko) * 2001-06-16 2003-08-21 삼성전자주식회사 캐쉬 메모리 및 이를 이용하는 마이크로 프로세서
JP2003196156A (ja) * 2001-12-28 2003-07-11 Fujitsu Ltd 情報処理装置および情報処理方法
US6944714B2 (en) * 2002-07-30 2005-09-13 Hewlett-Packard Development Company, L.P. Method and apparatus for saving microprocessor power when sequentially accessing the microprocessor's instruction cache
JP3834323B2 (ja) 2004-04-30 2006-10-18 日本電気株式会社 キャッシュメモリおよびキャッシュ制御方法
US20070156992A1 (en) * 2005-12-30 2007-07-05 Intel Corporation Method and system for optimizing latency of dynamic memory sizing
WO2006082551A1 (en) * 2005-02-07 2006-08-10 Nxp B.V. Data processing system and method of cache replacement
US20070043965A1 (en) * 2005-08-22 2007-02-22 Intel Corporation Dynamic memory sizing for power reduction
US7991955B2 (en) * 2006-12-13 2011-08-02 Advanced Micro Devices, Inc. Method and apparatus to achieve more level thermal gradient
JP4635063B2 (ja) 2008-03-11 2011-02-16 株式会社東芝 キャッシュメモリ制御回路及びプロセッサ
JP5142868B2 (ja) 2008-07-17 2013-02-13 株式会社東芝 キャッシュメモリ制御回路及びプロセッサ
US8347037B2 (en) 2008-10-22 2013-01-01 International Business Machines Corporation Victim cache replacement
US8209489B2 (en) 2008-10-22 2012-06-26 International Business Machines Corporation Victim cache prefetching
US8499124B2 (en) 2008-12-16 2013-07-30 International Business Machines Corporation Handling castout cache lines in a victim cache
US8225045B2 (en) 2008-12-16 2012-07-17 International Business Machines Corporation Lateral cache-to-cache cast-in
US8117397B2 (en) 2008-12-16 2012-02-14 International Business Machines Corporation Victim cache line selection
US8489819B2 (en) 2008-12-19 2013-07-16 International Business Machines Corporation Victim cache lateral castout targeting
US8949540B2 (en) 2009-03-11 2015-02-03 International Business Machines Corporation Lateral castout (LCO) of victim cache line in data-invalid state
US8285939B2 (en) 2009-04-08 2012-10-09 International Business Machines Corporation Lateral castout target selection
US8347036B2 (en) 2009-04-09 2013-01-01 International Business Machines Corporation Empirically based dynamic control of transmission of victim cache lateral castouts
US8327073B2 (en) 2009-04-09 2012-12-04 International Business Machines Corporation Empirically based dynamic control of acceptance of victim cache lateral castouts
US8312220B2 (en) 2009-04-09 2012-11-13 International Business Machines Corporation Mode-based castout destination selection
US9189403B2 (en) 2009-12-30 2015-11-17 International Business Machines Corporation Selective cache-to-cache lateral castouts
US8352683B2 (en) * 2010-06-24 2013-01-08 Intel Corporation Method and system to reduce the power consumption of a memory device
US9495299B2 (en) 2011-12-26 2016-11-15 Renesas Electronics Corporation Data processing device utilizing way selection of set associative cache memory based on select data such as parity data
US9396117B2 (en) * 2012-01-09 2016-07-19 Nvidia Corporation Instruction cache power reduction
US9547358B2 (en) 2012-04-27 2017-01-17 Nvidia Corporation Branch prediction power reduction
US9552032B2 (en) 2012-04-27 2017-01-24 Nvidia Corporation Branch prediction power reduction
US8943274B2 (en) * 2012-05-22 2015-01-27 Seagate Technology Llc Changing power state with an elastic cache
US9135182B2 (en) * 2012-06-01 2015-09-15 Semiconductor Energy Laboratory Co., Ltd. Central processing unit and driving method thereof
US8977817B2 (en) * 2012-09-28 2015-03-10 Apple Inc. System cache with fine grain power management
JP5954112B2 (ja) * 2012-10-24 2016-07-20 富士通株式会社 メモリ装置、演算処理装置、及びキャッシュメモリ制御方法
KR101490072B1 (ko) * 2014-01-28 2015-02-06 한양대학교 산학협력단 캐시의 전력 제어를 위한 장치 및 방법
US10719434B2 (en) 2014-12-14 2020-07-21 Via Alliance Semiconductors Co., Ltd. Multi-mode set associative cache memory dynamically configurable to selectively allocate into all or a subset of its ways depending on the mode
JP6207765B2 (ja) * 2014-12-14 2017-10-04 ヴィア アライアンス セミコンダクター カンパニー リミテッド モードに応じてセットの１つ又は複数を選択的に選択するように動的に構成可能であるマルチモード・セット・アソシエイティブ・キャッシュ・メモリ
EP3129886B1 (de) * 2014-12-14 2019-10-02 VIA Alliance Semiconductor Co., Ltd. Dynamische cacheersatzwegauswahl auf der basis von adressetikettbits
JP6149265B2 (ja) * 2016-04-05 2017-06-21 ルネサスエレクトロニクス株式会社 データ処理装置
US11507174B2 (en) * 2020-02-25 2022-11-22 Qualcomm Incorporated System physical address size aware cache memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5014195A (en) * 1990-05-10 1991-05-07 Digital Equipment Corporation, Inc. Configurable set associative cache with decoded data element enable lines
JPH04186595A (ja) * 1990-11-21 1992-07-03 Hitachi Ltd キャッシュメモリ装置
US5860127A (en) * 1995-06-01 1999-01-12 Hitachi, Ltd. Cache memory employing dynamically controlled data array start timing and a microcomputer using the same
JPH09223068A (ja) * 1996-02-15 1997-08-26 Toshiba Microelectron Corp キャッシュメモリ
US5848428A (en) * 1996-12-19 1998-12-08 Compaq Computer Corporation Sense amplifier decoding in a memory device to reduce power consumption
US5978282A (en) * 1997-04-03 1999-11-02 Texas Instruments Incorporated Low power line system and method
JPH1185617A (ja) * 1997-09-01 1999-03-30 Toshiba Corp コンピュータシステム
KR19990057856A (ko) * 1997-12-30 1999-07-15 김영환 저전력 캐쉬 메모리 장치

Also Published As

Publication number Publication date
EP1231539A3 (de) 2004-01-21
EP1231539A2 (de) 2002-08-14
EP1231539B1 (de) 2006-03-08
US20020112126A1 (en) 2002-08-15
KR100794973B1 (ko) 2008-01-16
KR20020066950A (ko) 2002-08-21
DE60117735T2 (de) 2006-08-17
JP2002236616A (ja) 2002-08-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee