DE60105787D1 - Prüfungsverfahren für integrierte Schaltungen - Google Patents

Prüfungsverfahren für integrierte Schaltungen

Info

Publication number
DE60105787D1
DE60105787D1 DE60105787T DE60105787T DE60105787D1 DE 60105787 D1 DE60105787 D1 DE 60105787D1 DE 60105787 T DE60105787 T DE 60105787T DE 60105787 T DE60105787 T DE 60105787T DE 60105787 D1 DE60105787 D1 DE 60105787D1
Authority
DE
Germany
Prior art keywords
integrated circuits
test methods
test
methods
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60105787T
Other languages
English (en)
Inventor
Giuseppe Tuttobene
Gregorio Giuseppe Di
Biagio Russo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SRL filed Critical STMicroelectronics SRL
Application granted granted Critical
Publication of DE60105787D1 publication Critical patent/DE60105787D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response
    • G01R31/31935—Storing data, e.g. failure memory
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Tests Of Electronic Circuits (AREA)
DE60105787T 2001-06-21 2001-06-21 Prüfungsverfahren für integrierte Schaltungen Expired - Lifetime DE60105787D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP01830417A EP1271169B1 (de) 2001-06-21 2001-06-21 Prüfungsverfahren für integrierte Schaltungen

Publications (1)

Publication Number Publication Date
DE60105787D1 true DE60105787D1 (de) 2004-10-28

Family

ID=8184583

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60105787T Expired - Lifetime DE60105787D1 (de) 2001-06-21 2001-06-21 Prüfungsverfahren für integrierte Schaltungen

Country Status (3)

Country Link
US (1) US6757632B2 (de)
EP (1) EP1271169B1 (de)
DE (1) DE60105787D1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7020572B2 (en) * 2004-08-13 2006-03-28 Agilent Technologies, Inc. Method for receiving and associating conditional dependent test results

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398197A (en) * 1991-10-06 1995-03-14 Mitsubishi Denki Kabushiki Kaisha Method of creating debug specification and test program creating specification
US5894424A (en) * 1997-05-15 1999-04-13 Matsushita Electrical Industrial Co., Ltd. Semiconductor testing apparatus
US6363507B1 (en) * 1998-10-19 2002-03-26 Teradyne, Inc. Integrated multi-channel analog test instrument architecture providing flexible triggering
US6512989B1 (en) * 1999-03-26 2003-01-28 Ltx Corporation Generating and controlling analog and digital signals on a mixed signal test system
US6466007B1 (en) * 2000-08-14 2002-10-15 Teradyne, Inc. Test system for smart card and indentification devices and the like

Also Published As

Publication number Publication date
US20020198674A1 (en) 2002-12-26
EP1271169A1 (de) 2003-01-02
EP1271169B1 (de) 2004-09-22
US6757632B2 (en) 2004-06-29

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Legal Events

Date Code Title Description
8332 No legal effect for de