DE60035994D1 - Verfahren zur Herstellung eines dünnen selbsttragenden Halbleitervorrichtungsfilms und einer dreidimensionalen Halbleitervorrichtung - Google Patents

Verfahren zur Herstellung eines dünnen selbsttragenden Halbleitervorrichtungsfilms und einer dreidimensionalen Halbleitervorrichtung

Info

Publication number
DE60035994D1
DE60035994D1 DE60035994T DE60035994T DE60035994D1 DE 60035994 D1 DE60035994 D1 DE 60035994D1 DE 60035994 T DE60035994 T DE 60035994T DE 60035994 T DE60035994 T DE 60035994T DE 60035994 D1 DE60035994 D1 DE 60035994D1
Authority
DE
Germany
Prior art keywords
semiconductor device
manufacturing
thin self
supporting
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60035994T
Other languages
English (en)
Other versions
DE60035994T2 (de
Inventor
Barbara Vasquez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE60035994D1 publication Critical patent/DE60035994D1/de
Publication of DE60035994T2 publication Critical patent/DE60035994T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE60035994T 2000-10-04 2000-10-04 Verfahren zur Herstellung eines dünnen selbsttragenden Halbleitervorrichtungsfilms und einer dreidimensionalen Halbleitervorrichtung Expired - Lifetime DE60035994T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP00121689A EP1195808B1 (de) 2000-10-04 2000-10-04 Verfahren zur Herstellung eines dünnen selbsttragenden Halbleitervorrichtungsfilms und einer dreidimensionalen Halbleitervorrichtung

Publications (2)

Publication Number Publication Date
DE60035994D1 true DE60035994D1 (de) 2007-09-27
DE60035994T2 DE60035994T2 (de) 2008-06-05

Family

ID=8170013

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60035994T Expired - Lifetime DE60035994T2 (de) 2000-10-04 2000-10-04 Verfahren zur Herstellung eines dünnen selbsttragenden Halbleitervorrichtungsfilms und einer dreidimensionalen Halbleitervorrichtung

Country Status (3)

Country Link
US (1) US6521512B2 (de)
EP (1) EP1195808B1 (de)
DE (1) DE60035994T2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6770495B1 (en) * 2003-01-15 2004-08-03 Advanced Micro Devices, Inc. Method for revealing active regions in a SOI structure for DUT backside inspection
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
US20050046034A1 (en) 2003-09-03 2005-03-03 Micron Technology, Inc. Apparatus and method for high density multi-chip structures
US6991946B1 (en) * 2003-11-05 2006-01-31 Advanced Micro Devices, Inc. Method and system for providing backside voltage contrast for silicon on insulator devices
US8214786B2 (en) * 2004-09-08 2012-07-03 Hewlett-Packard Development Company, L.P. Scalable, component-accessible, and highly interconnected three-dimensional component arrangement within a system
WO2008035261A1 (en) 2006-09-22 2008-03-27 Nxp B.V. Electronic device and method for making the same
US20080173972A1 (en) * 2007-01-19 2008-07-24 International Business Machines Corporation Method of wafer thinning
US8420530B2 (en) 2007-08-10 2013-04-16 Agency For Science, Technology And Research Nano-interconnects for atomic and molecular scale circuits
US9748106B2 (en) * 2016-01-21 2017-08-29 Micron Technology, Inc. Method for fabricating semiconductor package
CN107689326A (zh) * 2016-08-05 2018-02-13 上海新昇半导体科技有限公司 一种晶圆减薄方法及装置

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
DE4433845A1 (de) * 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
DE4433846C2 (de) * 1994-09-22 1999-06-02 Fraunhofer Ges Forschung Verfahren zur Herstellung einer vertikalen integrierten Schaltungsstruktur
DE19516487C1 (de) * 1995-05-05 1996-07-25 Fraunhofer Ges Forschung Verfahren zur vertikalen Integration mikroelektronischer Systeme
JP2976929B2 (ja) * 1997-05-30 1999-11-10 日本電気株式会社 半導体装置の製造方法
EP0926726A1 (de) * 1997-12-16 1999-06-30 STMicroelectronics S.r.l. Herstellungsverfahren und elektronische Anordnung mit einem Durchkontakt, der von der Vorder- auf die Rückseite reicht, für die Verbindung zu einer Unterlage
DE19846232A1 (de) 1998-09-03 2000-03-09 Fraunhofer Ges Forschung Verfahren zur Herstellung eines Halbleiterbauelements mit Rückseitenkontaktierung

Also Published As

Publication number Publication date
DE60035994T2 (de) 2008-06-05
EP1195808B1 (de) 2007-08-15
US20020048955A1 (en) 2002-04-25
EP1195808A1 (de) 2002-04-10
US6521512B2 (en) 2003-02-18

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition