DE60025789D1 - Logische eingebaute Selbstprüfung (LBIST) Steuerschaltungen, Systeme und Verfahren mit automatischer Bestimmung der maximalen Abtastkettenlänge - Google Patents

Logische eingebaute Selbstprüfung (LBIST) Steuerschaltungen, Systeme und Verfahren mit automatischer Bestimmung der maximalen Abtastkettenlänge

Info

Publication number
DE60025789D1
DE60025789D1 DE60025789T DE60025789T DE60025789D1 DE 60025789 D1 DE60025789 D1 DE 60025789D1 DE 60025789 T DE60025789 T DE 60025789T DE 60025789 T DE60025789 T DE 60025789T DE 60025789 D1 DE60025789 D1 DE 60025789D1
Authority
DE
Germany
Prior art keywords
lbist
systems
methods
chain length
control circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60025789T
Other languages
English (en)
Other versions
DE60025789T2 (de
Inventor
Graham G Hetherington
Anthony Fryars
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of DE60025789D1 publication Critical patent/DE60025789D1/de
Application granted granted Critical
Publication of DE60025789T2 publication Critical patent/DE60025789T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60025789T 1999-12-20 2000-11-24 Logische eingebaute Selbstprüfung (LBIST) Steuerschaltungen, Systeme und Verfahren mit automatischer Bestimmung der maximalen Abtastkettenlänge Expired - Lifetime DE60025789T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US17284599P 1999-12-20 1999-12-20
US172845P 1999-12-20
US09/696,326 US6654920B1 (en) 1999-12-20 2000-10-25 LBIST controller circuits, systems, and methods with automated maximum scan channel length
US696326 2000-10-25

Publications (2)

Publication Number Publication Date
DE60025789D1 true DE60025789D1 (de) 2006-04-13
DE60025789T2 DE60025789T2 (de) 2006-08-31

Family

ID=26868521

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60025789T Expired - Lifetime DE60025789T2 (de) 1999-12-20 2000-11-24 Logische eingebaute Selbstprüfung (LBIST) Steuerschaltungen, Systeme und Verfahren mit automatischer Bestimmung der maximalen Abtastkettenlänge

Country Status (3)

Country Link
US (1) US6654920B1 (de)
EP (1) EP1113279B1 (de)
DE (1) DE60025789T2 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715105B1 (en) * 2000-11-14 2004-03-30 Agilent Technologies, Inc. Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port
US20030074616A1 (en) * 2001-10-12 2003-04-17 Dorsey Michael C. ASIC BIST controller employing multiple clock domains
US6901543B2 (en) * 2001-10-12 2005-05-31 Sun Microsystems, Inc. Utilizing slow ASIC logic BIST to preserve timing integrity across timing domains
US6996760B2 (en) * 2001-10-12 2006-02-07 Sun Microsystems ASIC BIST employing stored indications of completion
US6981191B2 (en) * 2001-10-12 2005-12-27 Sun Microsystems, Inc. ASIC logic BIST employing registers seeded with differing primitive polynomials
US20030074619A1 (en) * 2001-10-12 2003-04-17 Dorsey Michael C. Memory bist employing a memory bist signature
US20030074618A1 (en) * 2001-10-12 2003-04-17 Dorsey Michael C. Dual mode ASIC BIST controller
US20030074620A1 (en) * 2001-10-12 2003-04-17 Dorsey Michael C. Configurable asic memory bist controller employing multiple state machines
JP2003344500A (ja) * 2002-05-29 2003-12-03 Nec Electronics Corp マクロテスト回路
JP4274806B2 (ja) * 2003-01-28 2009-06-10 株式会社リコー 半導体集積回路およびスキャンテスト法
US7506210B1 (en) 2003-06-26 2009-03-17 Xilinx, Inc. Method of debugging PLD configuration using boundary scan
KR100594257B1 (ko) * 2004-02-26 2006-06-30 삼성전자주식회사 내장형 셀프 테스트 회로를 가지는 ｓｏｃ 및 그 셀프테스트 방법
US7480843B1 (en) * 2004-09-29 2009-01-20 Xilinx, Inc. Configuration access from a boundary-scannable device
US7272761B2 (en) * 2004-11-04 2007-09-18 International Business Machines Corporation Method, system, and program product for controlling test data of a logic built-in self-test of an integrated circuit
US7272764B2 (en) * 2004-11-04 2007-09-18 International Business Machines Corporation Method, system, and program product for boundary I/O testing employing a logic built-in self-test of an integrated circuit
US7224638B1 (en) 2005-12-15 2007-05-29 Sun Microsystems, Inc. Reliability clock domain crossing
US7627065B2 (en) * 2005-12-21 2009-12-01 Sun Microsystems, Inc. Generating a clock crossing signal based on clock ratios
US20070266283A1 (en) * 2006-05-01 2007-11-15 Nec Laboratories America, Inc. Method and Apparatus for Testing an Integrated Circuit
TWI312075B (en) * 2006-11-30 2009-07-11 Ind Tech Res Inst Scan test data compression method and decoding apparatus for multiple-scan-chain designs
US7823035B2 (en) * 2007-05-15 2010-10-26 International Business Machines Corporation System and methods of balancing scan chains and inserting the balanced-length scan chains into hierarchically designed integrated circuits
US8205125B2 (en) * 2009-10-23 2012-06-19 Texas Instruments Incorporated Enhanced control in scan tests of integrated circuits with partitioned scan chains
US8856720B2 (en) 2013-01-03 2014-10-07 International Business Machines Corporation Test coverage of integrated circuits with masking pattern selection
US9052900B2 (en) 2013-01-29 2015-06-09 Oracle International Corporation Serdes fast retrain method upon exiting power saving mode
US9182445B2 (en) * 2013-05-06 2015-11-10 Broadcom Corporation Integrated circuit with toggle suppression logic
US9244756B1 (en) 2014-07-30 2016-01-26 International Business Machines Corporation Logic-built-in-self-test diagnostic method for root cause identification
US9798893B2 (en) 2015-01-29 2017-10-24 International Business Machines Corporation Secure format-preserving encryption of data fields
US9964591B2 (en) * 2016-04-19 2018-05-08 International Business Machines Corporation Implementing decreased scan data interdependence in on product multiple input signature register (OPMISR) through PRPG control rotation

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2839950B1 (de) * 1978-09-14 1979-10-25 Ibm Deutschland Einrichtung zur Feststellung der Laenge beliebiger Schieberegister
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US4959832A (en) * 1988-12-09 1990-09-25 International Business Machines Parallel pseudorandom pattern generator with varying phase shift
US5333139A (en) * 1992-12-30 1994-07-26 Intel Corporation Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain
US5642362A (en) * 1994-07-20 1997-06-24 International Business Machines Corporation Scan-based delay tests having enhanced test vector pattern generation
US6442723B1 (en) * 1999-05-12 2002-08-27 International Business Machines Corporation Logic built-in self test selective signature generation

Also Published As

Publication number Publication date
EP1113279B1 (de) 2006-02-01
US6654920B1 (en) 2003-11-25
EP1113279A2 (de) 2001-07-04
EP1113279A3 (de) 2003-11-12
DE60025789T2 (de) 2006-08-31

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