DE4190037T - - Google Patents
Info
- Publication number
- DE4190037T DE4190037T DE19914190037 DE4190037T DE4190037T DE 4190037 T DE4190037 T DE 4190037T DE 19914190037 DE19914190037 DE 19914190037 DE 4190037 T DE4190037 T DE 4190037T DE 4190037 T DE4190037 T DE 4190037T
- Authority
- DE
- Germany
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28158—Making the insulator
- H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
- H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8248—Combination of bipolar and field-effect technology
- H01L21/8249—Bipolar and MOS technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41708—Emitter or collector electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/019—Contacts of silicides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/136—Resistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/463,290 US5112761A (en) | 1990-01-10 | 1990-01-10 | Bicmos process utilizing planarization technique |
Publications (1)
Publication Number | Publication Date |
---|---|
DE4190037T true DE4190037T (US07498051-20090303-C00003.png) | 1992-12-10 |
Family
ID=23839593
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE19914190037 Withdrawn DE4190037T (US07498051-20090303-C00003.png) | 1990-01-10 | 1991-01-10 |
Country Status (6)
Families Citing this family (67)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5227317A (en) * | 1989-04-21 | 1993-07-13 | Hitachi, Ltd. | Method of manufacturing semiconductor integrated circuit bipolar transistor device |
IT1236601B (it) * | 1989-12-22 | 1993-03-18 | Sgs Thomson Microelectronics | Dispositivo a semiconduttore integrato di tipo eprom con connessioni metalliche di source e procedimento per la sua fabbricazione. |
JP3031966B2 (ja) * | 1990-07-02 | 2000-04-10 | 株式会社東芝 | 集積回路装置 |
US5278105A (en) * | 1992-08-19 | 1994-01-11 | Intel Corporation | Semiconductor device with dummy features in active layers |
US5466484A (en) * | 1993-09-29 | 1995-11-14 | Motorola, Inc. | Resistor structure and method of setting a resistance value |
US6057604A (en) * | 1993-12-17 | 2000-05-02 | Stmicroelectronics, Inc. | Integrated circuit contact structure having gate electrode protection for self-aligned contacts with zero enclosure |
JPH0845936A (ja) * | 1994-05-31 | 1996-02-16 | Texas Instr Inc <Ti> | ダミーリードを用いた高速lsi半導体装置およびその信頼性改善方法 |
TW272310B (en) * | 1994-11-09 | 1996-03-11 | At & T Corp | Process for producing multi-level metallization in an integrated circuit |
US5571733A (en) * | 1995-05-12 | 1996-11-05 | Micron Technology, Inc. | Method of forming CMOS integrated circuitry |
US5627097A (en) * | 1995-07-03 | 1997-05-06 | Motorola, Inc. | Method for making CMOS device having reduced parasitic capacitance |
US5530418A (en) * | 1995-07-26 | 1996-06-25 | Taiwan Semiconductor Manufacturing Company | Method for shielding polysilicon resistors from hydrogen intrusion |
US5830791A (en) * | 1995-09-06 | 1998-11-03 | Lg Semicon Co., Ltd. | Manufacturing process for a DRAM with a buried region |
JPH09139495A (ja) * | 1995-11-14 | 1997-05-27 | Nippon Steel Corp | 半導体装置およびその製造方法 |
US5808362A (en) * | 1996-02-29 | 1998-09-15 | Motorola, Inc. | Interconnect structure and method of forming |
US5723358A (en) * | 1996-04-29 | 1998-03-03 | Vlsi Technology, Inc. | Method of manufacturing amorphous silicon antifuse structures |
US5622884A (en) * | 1996-05-30 | 1997-04-22 | Winbond Electronics Corp. | Method for manufacturing a semiconductor memory cell and a polysilicon load resistor of the semiconductor memory cell |
US5811329A (en) * | 1996-06-03 | 1998-09-22 | Micron Technology, Inc. | Method of forming CMOS circuitry including patterning a layer of conductive material overlying field isolation oxide |
US5795829A (en) * | 1996-06-03 | 1998-08-18 | Advanced Micro Devices, Inc. | Method of high density plasma metal etching |
US6025268A (en) * | 1996-06-26 | 2000-02-15 | Advanced Micro Devices, Inc. | Method of etching conductive lines through an etch resistant photoresist mask |
US5863832A (en) | 1996-06-28 | 1999-01-26 | Intel Corporation | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system |
US5781445A (en) * | 1996-08-22 | 1998-07-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Plasma damage monitor |
US5705436A (en) * | 1996-08-26 | 1998-01-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for forming a poly load resistor |
US5681765A (en) * | 1996-10-28 | 1997-10-28 | National Semiconductor Corporation | Process for fabricating single polysilicon high performance BICMOS |
US5732014A (en) * | 1997-02-20 | 1998-03-24 | Micron Technology, Inc. | Merged transistor structure for gain memory cell |
US5899706A (en) * | 1997-06-30 | 1999-05-04 | Siemens Aktiengesellschaft | Method of reducing loading variation during etch processing |
JP2001510942A (ja) | 1997-07-15 | 2001-08-07 | インフィネオン テクノロジース アクチエンゲゼルシャフト | 半導体ゾーンに接触する方法 |
US5877051A (en) * | 1997-08-22 | 1999-03-02 | Micron Technology, Inc. | Methods of reducing alpha particle inflicted damage to SRAM cells, methods of forming integrated circuitry, and methods of forming SRAM cells |
US5977598A (en) * | 1997-09-23 | 1999-11-02 | Winbond Electronics Corporation | High load resistance implemented in a separate polysilicon layer with diffusion barrier therein for preventing load punch through therefrom |
US5998252A (en) * | 1997-12-29 | 1999-12-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of salicide and sac (self-aligned contact) integration |
US6100153A (en) * | 1998-01-20 | 2000-08-08 | International Business Machines Corporation | Reliable diffusion resistor and diffusion capacitor |
US5863820A (en) * | 1998-02-02 | 1999-01-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integration of sac and salicide processes on a chip having embedded memory |
US6015730A (en) * | 1998-03-05 | 2000-01-18 | Taiwan Semiconductor Manufacturing Company | Integration of SAC and salicide processes by combining hard mask and poly definition |
US6717233B1 (en) | 1999-02-01 | 2004-04-06 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for fabricating resistors within semiconductor integrated circuit devices |
US6274445B1 (en) * | 1999-02-03 | 2001-08-14 | Philips Semi-Conductor, Inc. | Method of manufacturing shallow source/drain junctions in a salicide process |
US6174824B1 (en) | 1999-03-04 | 2001-01-16 | International Business Machines Corporation | Post-processing a completed semiconductor device |
US6255200B1 (en) | 1999-05-17 | 2001-07-03 | International Business Machines Corporation | Polysilicon structure and process for improving CMOS device performance |
US6204148B1 (en) * | 1999-06-11 | 2001-03-20 | Advanced Micro Devices, Inc. | Method of making a semiconductor device having a grown polysilicon layer |
JP3384447B2 (ja) * | 1999-07-12 | 2003-03-10 | Nec化合物デバイス株式会社 | 吸収型光変調器およびその製造方法 |
US7125768B2 (en) * | 1999-08-25 | 2006-10-24 | Micron Technology, Inc. | Method for reducing single bit data loss in a memory circuit |
US6232194B1 (en) | 1999-11-05 | 2001-05-15 | Taiwan Semiconductor Manufacturing Company | Silicon nitride capped poly resistor with SAC process |
US6294433B1 (en) * | 2000-02-09 | 2001-09-25 | Advanced Micro Devices, Inc. | Gate re-masking for deeper source/drain co-implantation processes |
US6486066B2 (en) | 2001-02-02 | 2002-11-26 | Matrix Semiconductor, Inc. | Method of generating integrated circuit feature layout for improved chemical mechanical polishing |
JP3702212B2 (ja) * | 2001-09-28 | 2005-10-05 | 三菱重工業株式会社 | 軸シール機構及びタービン |
US6961915B2 (en) * | 2002-11-06 | 2005-11-01 | Lsi Logic Corporation | Design methodology for dummy lines |
US6867080B1 (en) * | 2003-06-13 | 2005-03-15 | Advanced Micro Devices, Inc. | Polysilicon tilting to prevent geometry effects during laser thermal annealing |
US7772653B1 (en) * | 2004-02-11 | 2010-08-10 | National Semiconductor Corporation | Semiconductor apparatus comprising bipolar transistors and metal oxide semiconductor transistors |
JP2005302999A (ja) * | 2004-04-12 | 2005-10-27 | Kawasaki Microelectronics Kk | 半導体集積回路 |
US7126199B2 (en) * | 2004-09-27 | 2006-10-24 | Intel Corporation | Multilayer metal gate electrode |
US7271079B2 (en) * | 2005-04-06 | 2007-09-18 | International Business Machines Corporation | Method of doping a gate electrode of a field effect transistor |
US20070108517A1 (en) * | 2005-11-12 | 2007-05-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | LDMOS with independently biased source |
US20090101988A1 (en) * | 2007-10-18 | 2009-04-23 | Texas Instruments Incorporated | Bipolar transistors with resistors |
US7785979B2 (en) * | 2008-07-15 | 2010-08-31 | International Business Machines Corporation | Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same |
US7755107B2 (en) * | 2008-09-24 | 2010-07-13 | Skyworks Solutions, Inc. | Bipolar/dual FET structure including enhancement and depletion mode FETs with isolated channels |
US8324686B2 (en) * | 2009-01-16 | 2012-12-04 | Infineon Technologies Austria Ag | Semiconductor device and method for manufacturing |
US8031100B2 (en) * | 2009-04-24 | 2011-10-04 | Intersil Americas Inc. | Fine resistance adjustment for polysilicon |
KR101078732B1 (ko) * | 2009-06-24 | 2011-11-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US8058125B1 (en) * | 2010-08-04 | 2011-11-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Poly resistor on a semiconductor device |
US8614152B2 (en) * | 2011-05-25 | 2013-12-24 | United Microelectronics Corp. | Gate structure and a method for forming the same |
US8927379B2 (en) | 2012-09-26 | 2015-01-06 | International Business Machines Corporation | Method to bridge extrinsic and intrinsic base by selective epitaxy in BiCMOS technology |
CN106062958B (zh) * | 2013-12-11 | 2019-11-19 | 理想能量有限公司 | 用于双向器件制造的系统和方法 |
US9761461B2 (en) * | 2014-04-16 | 2017-09-12 | Cirrus Logic, Inc. | Systems and methods for fabricating a polycrystaline semiconductor resistor on a semiconductor substrate |
US9412700B2 (en) * | 2014-10-15 | 2016-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacturing semiconductor device |
US20160276156A1 (en) * | 2015-03-16 | 2016-09-22 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and manufacturing process thereof |
US9825141B2 (en) * | 2015-05-26 | 2017-11-21 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Three dimensional monolithic LDMOS transistor |
US9595478B2 (en) * | 2015-06-12 | 2017-03-14 | Globalfoundries Inc. | Dummy gate used as interconnection and method of making the same |
TWI697096B (zh) * | 2016-06-14 | 2020-06-21 | 聯華電子股份有限公司 | 半導體元件及其製作方法 |
US10411085B2 (en) * | 2016-12-29 | 2019-09-10 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device and a method for fabricating the same |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4227944A (en) * | 1979-06-11 | 1980-10-14 | General Electric Company | Methods of making composite conductive structures in integrated circuits |
US4289846A (en) * | 1979-12-28 | 1981-09-15 | General Electric Company | Process for forming low-reactance interconnections on semiconductors |
US4569122A (en) * | 1983-03-09 | 1986-02-11 | Advanced Micro Devices, Inc. | Method of forming a low resistance quasi-buried contact |
US4581815A (en) * | 1984-03-01 | 1986-04-15 | Advanced Micro Devices, Inc. | Integrated circuit structure having intermediate metal silicide layer and method of making same |
US4677735A (en) * | 1984-05-24 | 1987-07-07 | Texas Instruments Incorporated | Method of providing buried contacts for N and P channel devices in an SOI-CMOS process using a single N+polycrystalline silicon layer |
US4670091A (en) * | 1984-08-23 | 1987-06-02 | Fairchild Semiconductor Corporation | Process for forming vias on integrated circuits |
US4735709A (en) * | 1985-07-05 | 1988-04-05 | Deister Concentrator Company, Inc. | Method and apparatus for concentration of minerals by froth flotation using dual aeration |
US4707456A (en) * | 1985-09-18 | 1987-11-17 | Advanced Micro Devices, Inc. | Method of making a planar structure containing MOS and bipolar transistors |
US4808548A (en) * | 1985-09-18 | 1989-02-28 | Advanced Micro Devices, Inc. | Method of making bipolar and MOS devices on same integrated circuit substrate |
US4688314A (en) * | 1985-10-02 | 1987-08-25 | Advanced Micro Devices, Inc. | Method of making a planar MOS device in polysilicon |
WO1987006764A1 (en) * | 1986-04-23 | 1987-11-05 | American Telephone & Telegraph Company | Process for manufacturing semiconductor devices |
JPH0628266B2 (ja) * | 1986-07-09 | 1994-04-13 | 株式会社日立製作所 | 半導体装置の製造方法 |
US4808555A (en) * | 1986-07-10 | 1989-02-28 | Motorola, Inc. | Multiple step formation of conductive material layers |
US4727046A (en) * | 1986-07-16 | 1988-02-23 | Fairchild Semiconductor Corporation | Method of fabricating high performance BiCMOS structures having poly emitters and silicided bases |
US4727045A (en) * | 1986-07-30 | 1988-02-23 | Advanced Micro Devices, Inc. | Plugged poly silicon resistor load for static random access memory cells |
KR890004420B1 (ko) * | 1986-11-04 | 1989-11-03 | 삼성반도체통신 주식회사 | 반도체 바이 씨 모오스장치의 제조방법 |
US4902640A (en) * | 1987-04-17 | 1990-02-20 | Tektronix, Inc. | High speed double polycide bipolar/CMOS integrated circuit process |
US4816423A (en) * | 1987-05-01 | 1989-03-28 | Texas Instruments Incorporated | Bicmos process for forming shallow npn emitters and mosfet source/drains |
US4912061A (en) * | 1988-04-04 | 1990-03-27 | Digital Equipment Corporation | Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer |
US4945070A (en) * | 1989-01-24 | 1990-07-31 | Harris Corporation | Method of making cmos with shallow source and drain junctions |
US4857481A (en) * | 1989-03-14 | 1989-08-15 | Motorola, Inc. | Method of fabricating airbridge metal interconnects |
US5041394A (en) * | 1989-09-11 | 1991-08-20 | Texas Instruments Incorporated | Method for forming protective barrier on silicided regions |
-
1990
- 1990-01-10 US US07/463,290 patent/US5112761A/en not_active Expired - Lifetime
-
1991
- 1991-01-10 DE DE19914190037 patent/DE4190037T/de not_active Withdrawn
- 1991-01-10 WO PCT/US1991/000211 patent/WO1991011019A1/en active Application Filing
- 1991-01-10 AU AU73139/91A patent/AU7313991A/en not_active Abandoned
- 1991-01-10 JP JP3504639A patent/JPH05505281A/ja active Pending
- 1991-01-28 US US07/647,494 patent/US5132237A/en not_active Expired - Lifetime
- 1991-01-28 US US07/647,709 patent/US5108945A/en not_active Expired - Lifetime
- 1991-01-28 US US07/647,707 patent/US5134083A/en not_active Expired - Lifetime
-
1992
- 1992-06-25 GB GB9213519A patent/GB2256527B/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB9213519D0 (en) | 1992-09-23 |
US5134083A (en) | 1992-07-28 |
JPH05505281A (ja) | 1993-08-05 |
US5132237A (en) | 1992-07-21 |
GB2256527B (en) | 1994-09-07 |
WO1991011019A1 (en) | 1991-07-25 |
US5108945A (en) | 1992-04-28 |
AU7313991A (en) | 1991-08-05 |
GB2256527A (en) | 1992-12-09 |
US5112761A (en) | 1992-05-12 |
Similar Documents
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8139 | Disposal/non-payment of the annual fee |