DE3879724D1 - Ram-speicheranordnung mit "nibble"-betrieb. - Google Patents

Ram-speicheranordnung mit "nibble"-betrieb.

Info

Publication number
DE3879724D1
DE3879724D1 DE8888101241T DE3879724T DE3879724D1 DE 3879724 D1 DE3879724 D1 DE 3879724D1 DE 8888101241 T DE8888101241 T DE 8888101241T DE 3879724 T DE3879724 T DE 3879724T DE 3879724 D1 DE3879724 D1 DE 3879724D1
Authority
DE
Germany
Prior art keywords
nibble
ram memory
memory arrangement
arrangement
ram
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888101241T
Other languages
English (en)
Other versions
DE3879724T2 (de
Inventor
Takashi C O Nec Corporat Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Memory Japan Ltd
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3879724D1 publication Critical patent/DE3879724D1/de
Publication of DE3879724T2 publication Critical patent/DE3879724T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
    • G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
DE8888101241T 1987-01-28 1988-01-28 Ram-speicheranordnung mit "nibble"-betrieb. Expired - Lifetime DE3879724T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62019293A JPS63184987A (ja) 1987-01-28 1987-01-28 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3879724D1 true DE3879724D1 (de) 1993-05-06
DE3879724T2 DE3879724T2 (de) 1993-07-08

Family

ID=11995381

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888101241T Expired - Lifetime DE3879724T2 (de) 1987-01-28 1988-01-28 Ram-speicheranordnung mit "nibble"-betrieb.

Country Status (4)

Country Link
US (1) US4875189A (de)
EP (1) EP0276852B1 (de)
JP (1) JPS63184987A (de)
DE (1) DE3879724T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69023258T2 (de) * 1989-03-15 1996-05-15 Matsushita Electronics Corp Halbleiter-Speichereinrichtung.
US5307314A (en) * 1991-07-15 1994-04-26 Micron Technology, Inc. Split read/write dynamic random access memory
US5506814A (en) * 1993-05-28 1996-04-09 Micron Technology, Inc. Video random access memory device and method implementing independent two WE nibble control
US5655113A (en) * 1994-07-05 1997-08-05 Monolithic System Technology, Inc. Resynchronization circuit for a memory system and method of operating same
TW424227B (en) * 1999-04-08 2001-03-01 Via Tech Inc Signal decoding device and method thereof
JP4067908B2 (ja) * 2002-08-08 2008-03-26 スパンション エルエルシー 半導体記憶装置の制御方法、および該半導体記憶装置
ITTO20021035A1 (it) * 2002-11-29 2004-05-30 St Microelectronics Srl Dispositivo di memoria non volatile a lettura e scrittura simulante.
US6906646B1 (en) * 2004-03-16 2005-06-14 Palmsource, Inc. Methods and devices for binary object serialization

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58146095A (ja) * 1982-02-24 1983-08-31 Oki Electric Ind Co Ltd ダイナミツク型メモリ回路
JPS58218097A (ja) * 1982-06-14 1983-12-19 Hitachi Ltd 高速半導体メモリ
JPS6087491A (ja) * 1983-10-19 1985-05-17 Fujitsu Ltd 記憶装置制御方式
US4618947B1 (en) * 1984-07-26 1998-01-06 Texas Instruments Inc Dynamic memory with improved address counter for serial modes
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access

Also Published As

Publication number Publication date
EP0276852A2 (de) 1988-08-03
DE3879724T2 (de) 1993-07-08
US4875189A (en) 1989-10-17
JPS63184987A (ja) 1988-07-30
EP0276852B1 (de) 1993-03-31
EP0276852A3 (en) 1990-10-24

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC CORP., TOKIO/TOKYO, JP

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8327 Change in the person/name/address of the patent owner

Owner name: ELPIDA MEMORY, INC., TOKYO, JP