DE3878345D1 - Bimosschaltung, faehig zum betrieb bei hoher geschwindigkeit mit niedrigem verbrauch. - Google Patents

Bimosschaltung, faehig zum betrieb bei hoher geschwindigkeit mit niedrigem verbrauch.

Info

Publication number
DE3878345D1
DE3878345D1 DE8888113356T DE3878345T DE3878345D1 DE 3878345 D1 DE3878345 D1 DE 3878345D1 DE 8888113356 T DE8888113356 T DE 8888113356T DE 3878345 T DE3878345 T DE 3878345T DE 3878345 D1 DE3878345 D1 DE 3878345D1
Authority
DE
Germany
Prior art keywords
bimo
switching
operate
high speed
low consumption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888113356T
Other languages
English (en)
Other versions
DE3878345T2 (de
Inventor
Toru Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62203156A external-priority patent/JPS6447124A/ja
Priority claimed from JP63020278A external-priority patent/JPH01194711A/ja
Application filed by NEC Corp filed Critical NEC Corp
Publication of DE3878345D1 publication Critical patent/DE3878345D1/de
Application granted granted Critical
Publication of DE3878345T2 publication Critical patent/DE3878345T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09448—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET in combination with bipolar transistors [BIMOS]
DE8888113356T 1987-08-17 1988-08-17 Bimosschaltung, faehig zum betrieb bei hoher geschwindigkeit mit niedrigem verbrauch. Expired - Fee Related DE3878345T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62203156A JPS6447124A (en) 1987-08-17 1987-08-17 Inverter circuit
JP63020278A JPH01194711A (ja) 1988-01-29 1988-01-29 インバータ回路

Publications (2)

Publication Number Publication Date
DE3878345D1 true DE3878345D1 (de) 1993-03-25
DE3878345T2 DE3878345T2 (de) 1993-05-27

Family

ID=26357190

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888113356T Expired - Fee Related DE3878345T2 (de) 1987-08-17 1988-08-17 Bimosschaltung, faehig zum betrieb bei hoher geschwindigkeit mit niedrigem verbrauch.

Country Status (3)

Country Link
US (1) US4926069A (de)
EP (1) EP0304035B1 (de)
DE (1) DE3878345T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2550138B2 (ja) * 1988-03-18 1996-11-06 株式会社日立製作所 バイポーラトランジスタと電界効果トランジスタとを有する半導体集積回路装置
JPH0239719A (ja) * 1988-07-29 1990-02-08 Fujitsu Ltd 半導体回路
JPH07120937B2 (ja) * 1988-11-08 1995-12-20 日本電気株式会社 インバータ回路
DE3904901A1 (de) * 1989-02-17 1990-08-23 Texas Instruments Deutschland Integrierte gegentakt-ausgangsstufe
EP0387461A1 (de) * 1989-03-14 1990-09-19 International Business Machines Corporation BICMOS-Schaltung mit vollem Spannungshub für logische Signale
DE69026534T2 (de) * 1989-05-15 1996-09-12 Texas Instruments Inc BICMOS-Hochleistungsschaltkreis mit voller Ausgangsspannungsschwingung
JPH02303216A (ja) * 1989-05-17 1990-12-17 Fujitsu Ltd 半導体集積回路
JPH0355914A (ja) * 1989-07-25 1991-03-11 Fujitsu Ltd 半導体装置
US5063304A (en) * 1990-04-27 1991-11-05 Texas Instruments Incorporated Integrated circuit with improved on-chip power supply control
US5140191A (en) * 1990-11-05 1992-08-18 Molorola, Inc. Low di/dt BiCMOS output buffer with improved speed
JP2570492B2 (ja) * 1990-11-28 1997-01-08 日本電気株式会社 半導体回路
JP3079515B2 (ja) * 1991-01-29 2000-08-21 株式会社東芝 ゲ−トアレイ装置及び入力回路及び出力回路及び降圧回路
US5132567A (en) * 1991-04-18 1992-07-21 International Business Machines Corporation Low threshold BiCMOS circuit
US5118972A (en) * 1991-06-13 1992-06-02 International Business Machines Corporation BiCMOS gate pull-down circuit
US5369309A (en) * 1991-10-30 1994-11-29 Harris Corporation Analog-to-digital converter and method of fabrication
US5994755A (en) * 1991-10-30 1999-11-30 Intersil Corporation Analog-to-digital converter and method of fabrication
US5254891A (en) * 1992-04-20 1993-10-19 International Business Machines Corporation BICMOS ECL circuit suitable for delay regulation
US5355035A (en) * 1993-01-08 1994-10-11 Vora Madhukar B High speed BICMOS switches and multiplexers
US6002268A (en) * 1993-01-08 1999-12-14 Dynachip Corporation FPGA with conductors segmented by active repeaters
US5552724A (en) * 1993-09-17 1996-09-03 Texas Instruments Incorporated Power-down reference circuit for ECL gate circuitry
DE102009001966A1 (de) 2009-03-30 2010-10-07 Evonik Röhm Gmbh Beschichtungszusammensetzung,(Meth)acryl-Polymer und Monomermischung zur Herstellung des(Meth)acryl-Polymers

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3274039D1 (en) * 1981-02-25 1986-12-04 Toshiba Kk Complementary mosfet logic circuit
KR890004212B1 (en) * 1983-07-08 1989-10-27 Fujitsu Ltd Complementary logic circuit
JPH0693626B2 (ja) * 1983-07-25 1994-11-16 株式会社日立製作所 半導体集積回路装置
EP0209805B1 (de) * 1985-07-22 1993-04-07 Hitachi, Ltd. Halbleitereinrichtung mit bipolarem Transistor und Isolierschicht-Feldeffekttransistor
US4675557A (en) * 1986-03-20 1987-06-23 Motorola Inc. CMOS voltage translator
JPH07120727B2 (ja) * 1987-03-27 1995-12-20 株式会社東芝 ＢｉＭＯＳ論理回路

Also Published As

Publication number Publication date
US4926069A (en) 1990-05-15
EP0304035A2 (de) 1989-02-22
EP0304035A3 (en) 1989-07-12
DE3878345T2 (de) 1993-05-27
EP0304035B1 (de) 1993-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP

8339 Ceased/non-payment of the annual fee