DE3871404D1 - Einrichtung zur ueberwachung des richtigen ablaufs eines datensicherungscoders. - Google Patents

Einrichtung zur ueberwachung des richtigen ablaufs eines datensicherungscoders.

Info

Publication number
DE3871404D1
DE3871404D1 DE8888100318T DE3871404T DE3871404D1 DE 3871404 D1 DE3871404 D1 DE 3871404D1 DE 8888100318 T DE8888100318 T DE 8888100318T DE 3871404 T DE3871404 T DE 3871404T DE 3871404 D1 DE3871404 D1 DE 3871404D1
Authority
DE
Germany
Prior art keywords
monitoring
data backup
correct operation
backup code
code
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888100318T
Other languages
English (en)
Inventor
Stefan Peter Jackowski
Ronald Brian Jenkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3871404D1 publication Critical patent/DE3871404D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Detection And Correction Of Errors (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
DE8888100318T 1987-01-29 1988-01-12 Einrichtung zur ueberwachung des richtigen ablaufs eines datensicherungscoders. Expired - Fee Related DE3871404D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/008,505 US4809273A (en) 1987-01-29 1987-01-29 Device for verifying operation of a checking code generator

Publications (1)

Publication Number Publication Date
DE3871404D1 true DE3871404D1 (de) 1992-07-02

Family

ID=21731987

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888100318T Expired - Fee Related DE3871404D1 (de) 1987-01-29 1988-01-12 Einrichtung zur ueberwachung des richtigen ablaufs eines datensicherungscoders.

Country Status (4)

Country Link
US (1) US4809273A (de)
EP (1) EP0280013B1 (de)
JP (1) JPS63197124A (de)
DE (1) DE3871404D1 (de)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2544385B2 (ja) * 1987-05-27 1996-10-16 株式会社日立製作所 通信制御装置
JPH01201736A (ja) * 1988-02-08 1989-08-14 Mitsubishi Electric Corp マイクロコンピュータ
US5170401A (en) * 1988-06-02 1992-12-08 Rockwell International Corporation High integrity single transmission line communication system for critical aviation information
JPH0212445A (ja) * 1988-06-30 1990-01-17 Mitsubishi Electric Corp 記憶装置
EP0411110A4 (en) * 1989-02-16 1993-02-24 Grumman Aerospace Corporation Very high speed error detection network
EP0436194A3 (en) * 1990-01-02 1992-12-16 National Semiconductor Corporation Media access controller
GB2242104B (en) * 1990-02-06 1994-04-13 Digital Equipment Int Method and apparatus for generating a frame check sequence
US5029133A (en) * 1990-08-30 1991-07-02 Hewlett-Packard Company VLSI chip having improved test access
CA2050123C (en) * 1990-10-11 1997-12-09 Subrahmanyam Dravida Apparatus and method for parallel generation of cyclic redundancy check (crc) codes
JP3260421B2 (ja) * 1992-06-30 2002-02-25 パイオニア株式会社 Ｃｄ−ｒｏｍ再生装置
US6047396A (en) * 1992-10-14 2000-04-04 Tm Patents, L.P. Digital data storage system including phantom bit storage locations
US5515506A (en) * 1994-08-23 1996-05-07 Hewlett-Packard Company Encoding and decoding of dual-ported RAM parity using one shared parity tree and within one clock cycle
US5754564A (en) * 1994-08-24 1998-05-19 Harris Corporation Method of continuous calculation of cyclic redundancy check
US5581566A (en) * 1995-01-06 1996-12-03 The Regents Of The Univ. Of California Office Of Technology Transfer High-performance parallel interface to synchronous optical network gateway
FR2759796B1 (fr) * 1997-02-19 2001-12-07 Bull Sa Dispositif et procede de detection d'erreurs sur un circuit integre comportant un port parallele serie
FR2765425B1 (fr) 1997-06-26 2000-06-09 Bull Sa Procede de detection d'erreurs sur une liaison serie d'un circuit integre et dispositif de mise en oeuvre du procede
EP2175559A1 (de) * 2002-04-22 2010-04-14 Fujitsu Limited Fehlerdetektionsdecodierer mit Wiederberechnung eines Divisionsrestes nach teilweiser Wiederübertragung einer Datenfolge
US20040098655A1 (en) * 2002-11-19 2004-05-20 Sharma Debendra Das Rolling CRC scheme for improved error detection
US7634614B2 (en) * 2003-01-13 2009-12-15 Sierra Logic Integrated-circuit implementation of a storage-shelf router and a path controller card for combined use in high-availability mass-storage-device shelves and that support virtual disk formatting
JP4634157B2 (ja) * 2005-01-17 2011-02-16 株式会社日立製作所 ストレージシステム
US7421640B2 (en) * 2005-08-17 2008-09-02 International Business Machines Corporation Method and apparatus for providing error correction capability to longitudinal position data
JP5089901B2 (ja) * 2006-03-28 2012-12-05 株式会社日立製作所 記憶制御装置及び記憶制御装置の制御方法
JP2008060552A (ja) 2006-08-02 2008-03-13 Osaka Univ 電子回路装置とその製造方法
DE102007028766A1 (de) * 2007-06-22 2008-12-24 Continental Teves Ag & Co. Ohg Prüfverfahren und elektronische Schaltung zur sicheren seriellen Übertragung von Daten
US8074146B2 (en) * 2007-09-28 2011-12-06 Broadcom Corporation Multiple cyclic redundancy check (CRC) engines for checking/appending CRCs during data transfers
JP2009271265A (ja) 2008-05-06 2009-11-19 Tomoegawa Paper Co Ltd 静電荷像現像用トナーおよびその製造方法
DE102009029979A1 (de) 2009-06-23 2010-12-30 Giesecke & Devrient Gmbh Verfahren zum Codieren und Decodieren von digitalen Daten, insbesondere von in einer Mikroprozessoreinheit verarbeiteten Daten
US20110219266A1 (en) * 2010-03-04 2011-09-08 Qualcomm Incorporated System and Method of Testing an Error Correction Module
US9960788B2 (en) * 2015-03-27 2018-05-01 Toshiba Memory Corporation Memory controller, semiconductor memory device, and control method for semiconductor memory device
US11048602B2 (en) * 2017-10-17 2021-06-29 SK Hynix Inc. Electronic devices
CN113176966B (zh) * 2021-03-12 2024-07-12 青芯半导体科技(上海)有限公司 一种检查spi接收数据有效性的系统及方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3889109A (en) * 1973-10-01 1975-06-10 Honeywell Inf Systems Data communications subchannel having self-testing apparatus
US4223382A (en) * 1978-11-30 1980-09-16 Sperry Corporation Closed loop error correct
JPS5924458B2 (ja) * 1980-09-24 1984-06-09 富士通株式会社 エラ−訂正回路のチェック方式
US4531213A (en) * 1982-03-03 1985-07-23 Sperry Corporation Memory through checking system with comparison of data word parity before and after ECC processing
US4520481A (en) * 1982-09-13 1985-05-28 Italtel--Societa Italiana Telecomunicazioni S.P.A. Data-handling system for the exchange of digital messages between two intercommunicating functional units
US4527269A (en) * 1983-02-08 1985-07-02 Ampex Corporation Encoder verifier
US4670876A (en) * 1985-05-15 1987-06-02 Honeywell Inc. Parity integrity check logic

Also Published As

Publication number Publication date
US4809273A (en) 1989-02-28
EP0280013B1 (de) 1992-05-27
JPS63197124A (ja) 1988-08-16
JPH0328094B2 (de) 1991-04-18
EP0280013A1 (de) 1988-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee