DE3870671D1 - Speicherleseverstaerker. - Google Patents

Speicherleseverstaerker.

Info

Publication number
DE3870671D1
DE3870671D1 DE8888400385T DE3870671T DE3870671D1 DE 3870671 D1 DE3870671 D1 DE 3870671D1 DE 8888400385 T DE8888400385 T DE 8888400385T DE 3870671 T DE3870671 T DE 3870671T DE 3870671 D1 DE3870671 D1 DE 3870671D1
Authority
DE
Germany
Prior art keywords
memory reader
differential stage
balancing
during
balancing phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888400385T
Other languages
English (en)
Inventor
Philippe Calzi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
SGS Thomson Microelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SA filed Critical SGS Thomson Microelectronics SA
Application granted granted Critical
Publication of DE3870671D1 publication Critical patent/DE3870671D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Static Random-Access Memory (AREA)
  • Holo Graphy (AREA)
  • Eye Examination Apparatus (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
DE8888400385T 1987-02-24 1988-02-19 Speicherleseverstaerker. Expired - Fee Related DE3870671D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8702371A FR2611330B1 (fr) 1987-02-24 1987-02-24 Amplificateur de lecture pour memoire

Publications (1)

Publication Number Publication Date
DE3870671D1 true DE3870671D1 (de) 1992-06-11

Family

ID=9348215

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888400385T Expired - Fee Related DE3870671D1 (de) 1987-02-24 1988-02-19 Speicherleseverstaerker.

Country Status (6)

Country Link
US (1) US4897569A (de)
EP (1) EP0281465B1 (de)
JP (1) JP2740796B2 (de)
AT (1) ATE75874T1 (de)
DE (1) DE3870671D1 (de)
FR (1) FR2611330B1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2663137B1 (fr) * 1990-06-12 1994-07-29 Sgs Thomson Microelectronics Dispositif electronique de connexion.
JPH0696582A (ja) * 1990-09-17 1994-04-08 Texas Instr Inc <Ti> メモリアレイアーキテクチャ
KR100263667B1 (ko) * 1997-12-30 2000-08-01 김영환 슈미트 트리거 회로
US6281731B1 (en) * 1999-10-27 2001-08-28 International Business Machines Corporation Control of hysteresis characteristic within a CMOS differential receiver
FR2823362B1 (fr) 2001-04-06 2005-03-11 St Microelectronics Sa Dispositif de lecture de cellules memoire
KR100559406B1 (ko) * 2004-10-15 2006-03-10 삼성전자주식회사 히스테리시스를 갖는 비교기 및 그것을 사용한 비교 방법
US7499344B2 (en) * 2006-01-05 2009-03-03 Infineon Technologies Ag Integrated circuit memory having a read circuit
US7333379B2 (en) * 2006-01-12 2008-02-19 International Business Machines Corporation Balanced sense amplifier circuits with adjustable transistor body bias

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5938670B2 (ja) * 1976-10-15 1984-09-18 日本電気株式会社 差信号増巾回路
JPS5947388B2 (ja) * 1977-03-04 1984-11-19 日本電気株式会社 増巾回路
US4110641A (en) * 1977-06-27 1978-08-29 Honeywell Inc. CMOS voltage comparator with internal hysteresis
US4301519A (en) * 1980-05-02 1981-11-17 International Business Machines Corporation Sensing technique for memories with small cells
JPS57208690A (en) * 1981-06-19 1982-12-21 Hitachi Ltd Semiconductor storage device
US4634890A (en) * 1984-09-06 1987-01-06 Thomson Components-Mostek Corporation Clamping circuit finding particular application between a single sided output of a computer memory and a differential amplifier sensing circuit
JPS61107594A (ja) * 1984-10-31 1986-05-26 Toshiba Corp センス増幅回路
JPS61116665A (ja) * 1984-11-12 1986-06-04 Fanuc Ltd 低電力消費形電圧比較回路
US4736117A (en) * 1986-11-14 1988-04-05 National Semiconductor Corporation VDS clamp for limiting impact ionization in high density CMOS devices
US4740760A (en) * 1986-11-14 1988-04-26 National Semiconductor Corporation Circuit technique for eliminating impact ionization in a differential pair used in an output stage

Also Published As

Publication number Publication date
FR2611330A1 (fr) 1988-08-26
JPS63227107A (ja) 1988-09-21
EP0281465B1 (de) 1992-05-06
US4897569A (en) 1990-01-30
JP2740796B2 (ja) 1998-04-15
EP0281465A1 (de) 1988-09-07
FR2611330B1 (fr) 1989-05-05
ATE75874T1 (de) 1992-05-15

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee