DE3855881D1 - Verfahren zur Herstellung einer Halbleiteranordnung mit Zwischenverbindungen, die über einer Halbleiterzone und über einer angrenzenden Isolationszone angebracht sind - Google Patents

Verfahren zur Herstellung einer Halbleiteranordnung mit Zwischenverbindungen, die über einer Halbleiterzone und über einer angrenzenden Isolationszone angebracht sind

Info

Publication number
DE3855881D1
DE3855881D1 DE3855881T DE3855881T DE3855881D1 DE 3855881 D1 DE3855881 D1 DE 3855881D1 DE 3855881 T DE3855881 T DE 3855881T DE 3855881 T DE3855881 T DE 3855881T DE 3855881 D1 DE3855881 D1 DE 3855881D1
Authority
DE
Germany
Prior art keywords
zone
semiconductor
over
interconnections
producing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3855881T
Other languages
English (en)
Other versions
DE3855881T2 (de
Inventor
Blanken Hubertus Johannes Den
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronics NV filed Critical Philips Electronics NV
Publication of DE3855881D1 publication Critical patent/DE3855881D1/de
Application granted granted Critical
Publication of DE3855881T2 publication Critical patent/DE3855881T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/105—Masks, metal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/926—Dummy metallization

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE3855881T 1987-05-01 1988-04-26 Verfahren zur Herstellung einer Halbleiteranordnung mit Zwischenverbindungen, die über einer Halbleiterzone und über einer angrenzenden Isolationszone angebracht sind Expired - Fee Related DE3855881T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8701032A NL8701032A (nl) 1987-05-01 1987-05-01 Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.

Publications (2)

Publication Number Publication Date
DE3855881D1 true DE3855881D1 (de) 1997-05-28
DE3855881T2 DE3855881T2 (de) 1997-11-06

Family

ID=19849941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855881T Expired - Fee Related DE3855881T2 (de) 1987-05-01 1988-04-26 Verfahren zur Herstellung einer Halbleiteranordnung mit Zwischenverbindungen, die über einer Halbleiterzone und über einer angrenzenden Isolationszone angebracht sind

Country Status (7)

Country Link
US (1) US4973562A (de)
EP (1) EP0289089B1 (de)
JP (1) JPS63285954A (de)
KR (1) KR0163943B1 (de)
CN (1) CN1011749B (de)
DE (1) DE3855881T2 (de)
NL (1) NL8701032A (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
JP3022744B2 (ja) * 1995-02-21 2000-03-21 日本電気株式会社 半導体装置及びその製造方法
US6191484B1 (en) * 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
US5593919A (en) * 1995-09-05 1997-01-14 Motorola Inc. Process for forming a semiconductor device including conductive members
JP2894254B2 (ja) * 1995-09-20 1999-05-24 ソニー株式会社 半導体パッケージの製造方法
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
US6486066B2 (en) * 2001-02-02 2002-11-26 Matrix Semiconductor, Inc. Method of generating integrated circuit feature layout for improved chemical mechanical polishing
JP3971213B2 (ja) * 2002-03-11 2007-09-05 アルプス電気株式会社 キーボード入力装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4267012A (en) * 1979-04-30 1981-05-12 Fairchild Camera & Instrument Corp. Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer
GB8316476D0 (en) * 1983-06-16 1983-07-20 Plessey Co Plc Producing layered structure
US4486946A (en) * 1983-07-12 1984-12-11 Control Data Corporation Method for using titanium-tungsten alloy as a barrier metal in silicon semiconductor processing
US4470874A (en) * 1983-12-15 1984-09-11 International Business Machines Corporation Planarization of multi-level interconnected metallization system
US4670091A (en) * 1984-08-23 1987-06-02 Fairchild Semiconductor Corporation Process for forming vias on integrated circuits
US4708767A (en) * 1984-10-05 1987-11-24 Signetics Corporation Method for providing a semiconductor device with planarized contacts
US4541169A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making studs for interconnecting metallization layers at different levels in a semiconductor chip
US4614021A (en) * 1985-03-29 1986-09-30 Motorola, Inc. Pillar via process
GB8518231D0 (en) * 1985-07-19 1985-08-29 Plessey Co Plc Producing layered structures
JPS6289331A (ja) * 1985-10-16 1987-04-23 Toshiba Corp 微細パタ−ンの加工方法
NL8600021A (nl) * 1986-01-08 1987-08-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op een halfgeleiderlichaam een metallisatie met een dikke aansluitelektrode wordt aangebracht.
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US4873565A (en) * 1987-11-02 1989-10-10 Texas Instruments Incorporated Method and apparatus for providing interconnection between metallization layers on semiconductor devices

Also Published As

Publication number Publication date
JPH0580150B2 (de) 1993-11-08
KR0163943B1 (ko) 1999-02-01
EP0289089A1 (de) 1988-11-02
NL8701032A (nl) 1988-12-01
JPS63285954A (ja) 1988-11-22
CN88103212A (zh) 1988-11-30
KR880014660A (ko) 1988-12-24
CN1011749B (zh) 1991-02-20
US4973562A (en) 1990-11-27
EP0289089B1 (de) 1997-04-23
DE3855881T2 (de) 1997-11-06

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN, N

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee